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Patent # Description
US-9,564,535 Semiconductor device, display device including the semiconductor device, display module including the display...
A change in electrical characteristics is inhibited and reliability is improved in a semiconductor device using a transistor including an oxide semiconductor....
US-9,564,534 Transistor and display device using the same
The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap...
US-9,564,532 Array substrate and method of fabricating the same
An array substrate including a substrate including a pixel region; a gate line on the substrate; a gate electrode on the substrate and connected to the gate...
US-9,564,531 Thin film transistors, methods of manufacturing thin film transistors, and semiconductor device including thin...
Thin film transistors including a semiconductor channel disposed between a drain electrode and a source electrode; and a gate insulating layer disposed between...
US-9,564,530 Integrated circuit structure and method with solid phase diffusion
The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate; a...
US-9,564,529 Method for fabricating a strained structure and structure formed
A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate....
US-9,564,528 Semiconductor device and manufacturing method thereof
A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper...
US-9,564,527 Semiconductor device and manufacturing method of semiconductor device
A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor...
US-9,564,526 Group III nitride integration with CMOS technology
A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The...
US-9,564,525 Compound semiconductor device
A compound semiconductor device includes: a substrate; and a buffer layer, a first carrier supply layer, a first spacer layer, a channel layer, a second spacer...
US-9,564,524 Semiconductor device and method
A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device...
US-9,564,523 Non-linear spin-orbit interaction devices and methods for current-to-spin conversion and amplification of...
The present invention is notably directed to a spin-orbit coupled device. This device comprises a confinement part. It further includes a circuitry, having an...
US-9,564,522 Nanowire structures having non-discrete source and drain regions
Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked...
US-9,564,521 Semiconductor device comprising ferroelectric elements and fast high-K metal gate transistors
A semiconductor device comprises a first and second circuit element. The first circuit element comprises a first electrode structure including a first high-k...
US-9,564,520 Method of forming semiconductor device
A method of forming a semiconductor device is disclosed. A sacrificial oxide layer is formed on a substrate having first and second areas. Using a photoresist...
US-9,564,519 Non-volatile memory devices and manufacturing methods thereof
There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of...
US-9,564,518 Method and apparatus for source-drain junction formation in a FinFET with in-situ doping
A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process...
US-9,564,517 Method for manufacturing semiconductor device
To provide a manufacturing method of a highly reliable TFT, by which a more refined pattern can be formed through a process using four or three masks, and a...
US-9,564,516 Method of making integrated MOSFET-schottky diode device with reduced source and body kelvin contact impedance...
A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a...
US-9,564,515 Semiconductor device having super junction structure and method for manufacturing the same
A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a first trench, a first doped...
US-9,564,514 Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels
An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes...
US-9,564,513 Epitaxy in semiconductor structure and manufacturing method thereof
A semiconductor structure including a semiconductor substrate is provided. The semiconductor substrate includes a surface. A gate structure is provided on the...
US-9,564,512 Fin field-effect transistor and fabrication method thereof
A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a...
US-9,564,511 Oxidation and etching post metal gate CMP
A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by...
US-9,564,510 Method of fabricating a MOSFET with an undoped channel
A method of fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating on a substrate a semiconductor structure having a dummy...
US-9,564,509 Method of fabricating an integrated circuit device
A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a...
US-9,564,508 Device isolation with improved thermal conductivity
A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a...
US-9,564,507 Interlayer dielectric layer with two tensile dielectric layers
A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the...
US-9,564,506 Low end parasitic capacitance FinFET
Embodiments of the present invention provide methods for fabricating a semiconductor device. One method may include providing a semiconductor substrate with...
US-9,564,505 Changing effective work function using ion implantation during dual work function metal gate integration
Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high...
US-9,564,504 Semiconductor device and method of manufacturing semiconductor device
A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a...
US-9,564,503 Semiconductor device and method of manufacturing semiconductor device
A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a...
US-9,564,502 Techniques for multiple gate workfunctions for a nanowire CMOS technology
In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a...
US-9,564,501 Reduced trench profile for a gate
The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls...
US-9,564,500 Fully-depleted SOI MOSFET with U-shaped channel
A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that...
US-9,564,499 Three-dimensional semiconductor memory devices and methods of fabricating the same
Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure...
US-9,564,498 Transistor with elevated drain termination
According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also...
US-9,564,497 High voltage field effect transitor finger terminations
A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed....
US-9,564,496 Process for treating a substrate using a luminous flux of determined wavelength, and corresponding substrate
A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the...
US-9,564,495 Semiconductor device with a semiconductor body containing hydrogen-related donors
A semiconductor device includes a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors. A concentration profile of...
US-9,564,494 Enhanced defect reduction for heteroepitaxy by seed shape engineering
A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the...
US-9,564,493 Devices having a semiconductor material that is semimetal in bulk and methods of forming the same
Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example...
US-9,564,492 Group III-V device with a selectively modified impurity concentration
There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body...
US-9,564,491 Semiconductor device
According to one embodiment, a semiconductor device includes an n-type semiconductor layer, a first electrode, and a nitride semiconductor layer. The n-type...
US-9,564,490 Apparatus and methods for forming a modulation doped non-planar transistor
Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors...
US-9,564,489 Multiple gate field-effect transistors having oxygen-scavenged gate stack
A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric...
US-9,564,488 Strained isolation regions
A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a...
US-9,564,487 Dual vertical channel
Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor...
US-9,564,486 Self-aligned dual-height isolation for bulk FinFET
A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group...
US-9,564,485 Switch driving circuit, inverter apparatus and power steering apparatus
A switch driving circuit electrically opens and closes a switch circuit including two N-channel type semiconductor switching elements series connected in a...
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