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Patent # Description
US-9,564,434 Semiconductor device with body spacer at the bottom of the fin and method for manufacturing the same
A semiconductor device and a method of manufacturing the same are disclosed. In one aspect, the method includes forming a first semiconductor layer and a second...
US-9,564,433 Semiconductor device with improved contact structure and method of forming same
A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact...
US-9,564,432 3D semiconductor device and structure
A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation...
US-9,564,431 Semiconductor structures and methods for multi-level work function
A semiconductor structure is provided comprising a vertical channel structure extending from a substrate and formed as a channel between a source region and a...
US-9,564,430 Macro-transistor devices
Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to...
US-9,564,429 Lateral bipolar sensor with sensing signal amplification
An integrated sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second bipolar junction...
US-9,564,428 Forming metal-insulator-metal capacitor
A method for fabricating a semiconductor device comprises forming a first sacrificial gate stack on a substrate, depositing an insulator layer on the substrate,...
US-9,564,427 Schottky diodes for replacement metal gate integrated circuits
An integrated circuit and method with a metal gate transistor and with a Schottky diode where the metal used to form the Schottky diode is the metal used to...
US-9,564,426 Semiconductor device and method of manufacturing the same
Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor...
US-9,564,425 Integrated transistor structure having a power transistor and a bipolar transistor
An integrated transistor structure includes an epitaxial layer on a semiconductor substrate, a power transistor formed in a first region of the epitaxial layer...
US-9,564,424 ESD device and structure therefor
In one embodiment, an ESD device is configured to include a trigger device that assists in forming a trigger of the ESD device. The trigger device is configured...
US-9,564,423 Power package with integrated magnetic field sensor
A power semiconductor package includes a substrate having a plurality of metal leads, a power semiconductor die attached to a first one of the leads and a...
US-9,564,422 Light emitting device and light emitting device package
A light emitting device according to the embodiment includes a support substrate; a first light emitting structure disposed on the support substrate and...
US-9,564,421 Semiconductor device
A semiconductor device includes a first substrate, a second substrate stacked over the first substrate, and a pillar member extending obliquely between the...
US-9,564,420 Functional block stacked 3DIC and method of making same
An embodiment device package includes a fan-out redistribution layer (RDL), a device over and bonded to the fan-out RDL, and a molding compound over the fan-out...
US-9,564,419 Semiconductor package structure and method for manufacturing the same
A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure comprises a substrate, a first chip,...
US-9,564,418 Interconnect structures with intermetallic palladium joints and associated systems and methods
Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes...
US-9,564,417 Multi-stacked structures of semiconductor packages
A multi-stacked structure of semiconductor packages includes a plurality of substrates stacked in a vertical direction, semiconductor packages mounted on each...
US-9,564,416 Package structures and methods of forming the same
Packages structure and methods of forming them are discussed. A structure includes a first die, a first encapsulant at least laterally encapsulating the first...
US-9,564,415 Semiconductor package device having passive energy components
A semiconductor package device is disclosed that includes a passive energy component integrated therein. In an implementation, the semiconductor package device...
US-9,564,414 Three dimensional device integration method and integrated device
A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element;...
US-9,564,413 Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus
A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the...
US-9,564,412 Shaped and oriented solder joints
The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic...
US-9,564,411 Semiconductor package and method of manufacturing the same
Disclosed herein is a semiconductor package having a fan-out structure in which a semiconductor chip is buried by an encapsulation member and an external...
US-9,564,410 Semiconductor devices having metal bumps with flange
A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over...
US-9,564,409 Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of...
A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each...
US-9,564,408 Space transformer
An apparatus including a planar semiconductor substrate including a plurality of devices and a first pattern of electrical contacts formed on the first surface...
US-9,564,407 Crosstalk polarity reversal and cancellation through substrate material
Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane....
US-9,564,406 Battery protection package and process of making the same
The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery...
US-9,564,405 Substrate opening formation in semiconductor devices
Radio-frequency (RF) devices are fabricated by providing a field-effect transistor (FET) formed over an oxide layer, forming one or more electrical connections...
US-9,564,404 System, method and apparatus to relieve stresses in a semiconductor wafer caused by uneven internal...
Systems and methods for forming semiconductor wafers with wafer support structures includes: multiple semiconductor devices formed in multiple semiconductor...
US-9,564,403 Magnetic shielding of perpendicular STT-MRAM
A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A...
US-9,564,402 Method and apparatus for creating and placing a micro message
Silicon processing technology is used to generate an array of micro messages. These micro messages can contain at least one stick figure, or at least one word,...
US-9,564,401 Method for thinning, metalizing, and dicing a semiconductor wafer, and semiconductor device made using the method
There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by...
US-9,564,400 Methods of forming stacked microelectronic dice embedded in a microelectronic substrate
Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one...
US-9,564,399 Solid state image sensor and method for manufacturing the same
A method of manufacturing a solid state image sensor is provided. The method includes forming electrically conductive layer and an interlayer insulation film...
US-9,564,398 Chemical direct pattern plating interconnect metallization and metal structure produced by the same
A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an...
US-9,564,397 Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer...
US-9,564,396 Semiconductor device and process
A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive...
US-9,564,395 Bonding pad arrangment design for multi-die semiconductor package structure
A semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area...
US-9,564,394 Methods and apparatus for reducing spatial overlap between routing wires
An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may include a predetermined routing of multiple wires on...
US-9,564,393 Semiconductor device package and method of making the same
A semiconductor device package includes a substrate and a semiconductor device disposed on a surface of the substrate. The semiconductor device includes a first...
US-9,564,392 Printed wiring board and semiconductor package
A printed wiring board includes a resin insulating layer, a wiring conductor layer embedded in the insulating layer such that the conductor layer has a first...
US-9,564,391 Thermal enhanced package using embedded substrate
An integrated circuit (IC) device is provided. The IC device includes an IC die having opposing first and second surfaces, a carrier coupled to the first...
US-9,564,390 Package structure and fabrication method thereof
A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric...
US-9,564,389 Semiconductor package with integrated die paddles for power stage
In one implementation, a semiconductor package includes a first conductive carrier including a first die paddle of the semiconductor package, and a control...
US-9,564,388 Semiconductor device having a plurality of circuits arranged on a side of a semiconductor chip
A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first...
US-9,564,387 Semiconductor package having routing traces therein
A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more...
US-9,564,386 Semiconductor package with structures for cooling fluid retention
A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from...
US-9,564,385 Package for a semiconductor device
A package for a semiconductor device or circuit comprises a semiconductor switch module having a metallic base on an exterior side and metallic pads. A sealed...
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