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Patent # Description
US-9,564,384 Plastic cooler for semiconductor modules
A cooling apparatus includes a plurality of discrete modules and a plastic housing. Each module includes a semiconductor die encapsulated by a mold compound, a...
US-9,564,383 Low-K dielectric layer and porogen
A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The...
US-9,564,382 Test structure for determining overlay accuracy in semiconductor devices using resistance measurement
Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor...
US-9,564,381 Apparatus and method to monitor die edge defects
Described is an apparatus comprising: an input pad; an output pad; a wire, coupled to the input pad and the output pad, the wire positioned at a periphery of a...
US-9,564,380 Marker pattern for enhanced failure analysis resolution
A marker pattern for enhancing resolution of a defect location along an axis in semiconductor defect analysis, and in particular, a marker pattern providing...
US-9,564,379 Via chains for defect localization
Via chain and serpentine/comb test structures are in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a...
US-9,564,378 Detection of lost wafer from spinning chuck
The disclosure relates to systems and methods for detecting when a microelectronic substrate is no longer properly secured or lost from a rotating chuck. A...
US-9,564,377 Peak-based endpointing for chemical mechanical polishing
A polishing system receives one or more target parameters for a selected peak in a spectrum of light, polishes a substrate, measures a current spectrum of light...
US-9,564,376 Semiconductor process
The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a...
US-9,564,375 Structures and methods for extraction of device channel width
Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of...
US-9,564,374 Forming method and method of manufacturing article
The present invention provides a forming method of forming a through electrode, in a second substrate joined on a first substrate having an electrode pad, to...
US-9,564,373 Forming a CMOS with dual strained channels
The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and...
US-9,564,372 Dual liner silicide
A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate...
US-9,564,371 Method for forming semiconductor device
A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality...
US-9,564,370 Effective device formation for advanced technology nodes with aggressive fin-pitch scaling
After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed...
US-9,564,369 Methods of manufacturing semiconductor devices including device isolation processes
Methods are provided for manufacturing semiconductor devices include forming a first fin protruding on a substrate and extending in a first direction; forming...
US-9,564,368 Semiconductor device and method of fabricating the same
A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming...
US-9,564,367 Methods of forming different FinFET devices with different threshold voltages and integrated circuit products...
One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin...
US-9,564,366 Method and apparatus for plasma dicing a semi-conductor wafer
The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma...
US-9,564,365 Method of singulating semiconductor wafer having back layer
In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the...
US-9,564,364 Semiconductor device, semiconductor package, method for manufacturing semiconductor device, and method for...
A semiconductor device includes a semiconductor substrate, which includes a through hole that extends through the semiconductor substrate. An insulative layer...
US-9,564,363 Method of forming butted contact
A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate structure over a substrate, forming a source/drain feature...
US-9,564,362 Interconnects based on subtractive etching of silver
A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a...
US-9,564,361 Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a...
US-9,564,360 Substrate processing method and method of manufacturing semiconductor device
An object of the present invention is to provide a method which enable a material to be fully embedded into a recess portion with a deposition film left in the...
US-9,564,359 Conductive structure and method of forming the same
Conductive structures and method of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive structure includes providing a...
US-9,564,358 Forming reliable contacts on tight semiconductor pitch
A method of forming a semiconductor device includes forming a trench in a passivating layer between neighboring fins. A barrier is formed in the trench....
US-9,564,357 Method of forming semiconductor device using etch stop layer
A semiconductor device and method of formation are provided. A semiconductor device includes a first material comprising STI adjacent a fin. The STI is...
US-9,564,356 Self-forming metal barriers
A technique includes applying a liquid dielectric composition onto a substrate, where the composition includes metal ions, at least partially curing the...
US-9,564,355 Interconnect structure for semiconductor devices
An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider...
US-9,564,354 Via-hole etching method
The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an...
US-9,564,353 FinFETs with reduced parasitic capacitance and methods of forming the same
An integrated circuit structure includes a semiconductor substrate, a semiconductor strip over a portion of the semiconductor substrate, and a Shallow Trench...
US-9,564,352 Method for fabricating semiconductor device including isolation layer
A semiconductor device includes a first isolation layer formed in a trench in a substrate. The isolation layer includes a first oxide layer formed in the trench...
US-9,564,351 Positioning frame structure
A positioning frame structure for the centering and positioning of an IC is disclosed, in which the positioning frame structure comprises an IC carrier having a...
US-9,564,350 Method and apparatus for storing and transporting semiconductor wafers in a vacuum pod
Methodology and system for using vacuum pods to store/transport semiconductor wafers to efficiently reduce contamination of the wafers while reducing cost,...
US-9,564,349 Rapid thermal processing chamber with micro-positioning system
Methods and apparatus for rapid thermal processing of a planar substrate including axially aligning the substrate with a substrate support or with an...
US-9,564,348 Shutter blade and robot blade with CTE compensation
Processing chamber shutter blade and robot blade assemblies are constructed to eliminate thermal effects on the placement of elements in processing chambers....
US-9,564,347 Liquid processing apparatus and liquid processing method
A liquid processing apparatus including: a second housing; a first housing capable of being brought into contact with the second housing; a holding part...
US-9,564,346 Package carrier, semiconductor package, and process for fabricating same
A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a...
US-9,564,345 Semiconductor device and manufacturing method thereof
A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The...
US-9,564,344 Ultra low silicon loss high dose implant strip
Improved methods for stripping photoresist and removing ion implant related residues from a work piece surface are provided. According to various embodiments,...
US-9,564,343 Method of manufacturing semiconductor devices
A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a...
US-9,564,342 Method for controlling etching in pitch doubling
Embodiments of the invention describe a method for controlling etching in pitch doubling. According to one embodiment, the method includes receiving a substrate...
US-9,564,341 Gas-phase silicon oxide selective etch
A method of etching silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using anhydrous vapor-phase HF. The HF is...
US-9,564,340 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a plurality of active fins over a semiconductor substrate, sequentially forming first and...
US-9,564,339 Etch resistant alumina based coatings
Method of forming a protective hard mask layer on a substrate in a semiconductor etch process, comprising the step of applying by solution deposition on the...
US-9,564,338 Silicon-selective removal
A method of etching exposed silicon on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote...
US-9,564,337 Polishing liquid and method for polishing substrate using the polishing liquid
Provided is a polishing liquid including cerium oxide particles, an organic acid A, a polymer compound B having a carboxyl acid group or a carboxylate group,...
US-9,564,336 NOR flash device manufacturing method
An embodiment of a NOR Flash device manufacturing method includes: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming...
US-9,564,335 Method for improving quality of spalled material layers
Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture...
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