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Patent # Description
US-9,564,233 Open block source bias adjustment for an incompletely programmed block of a nonvolatile storage device
Apparatuses, systems, methods, and computer program products are disclosed for adjusting a voltage level for a write operation on a partially programmed block...
US-9,564,232 Semiconductor memory device
Provided herein is a semiconductor memory device including a memory cell array including a drain select transistor and a plurality of memory cells, a voltage...
US-9,564,231 Non-volatile memory device and corresponding operating method with stress reduction
A non-volatile memory device includes a memory array with memory cells arranged in rows and columns. Each cell has respective current-conduction regions and a...
US-9,564,230 Semiconductor memory device and method of operating the same
A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array configured to...
US-9,564,229 Nonvolatile memory device and method of programming the same
In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a...
US-9,564,228 Semiconductor memory device and memory system
A semiconductor memory device includes a memory cell, and a control circuit configured to execute a writing operation on the memory cell in response to a write...
US-9,564,227 Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays
A sensing voltage may be applied to a particular memory cell that is in a particular layer of a plurality of layers of memory cells. While the sensing voltage...
US-9,564,226 Smart verify for programming non-volatile memory
Techniques are provided for reducing current consumption while programming non-volatile storage. A smart verify is performed using a subset of memory cells. By...
US-9,564,225 Pulse control for non-volatile memory
A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline...
US-9,564,224 Semiconductor device
A semiconductor device according to an embodiment comprises: a field effect transistor comprising a semiconductor layer and a gate electrode; a wiring line...
US-9,564,223 Semiconductor device
Disclosed is a semiconductor device, including: a memory block including a plurality of memory strings, each of the memory strings including a drain select...
US-9,564,222 Command signal management in integrated circuit devices
Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic...
US-9,564,221 Non-volatile memory device having vertical structure and method of operating the same
A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory...
US-9,564,220 Semiconductor device
A semiconductor device includes memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of...
US-9,564,219 Current based detection and recording of memory hole-interconnect spacing defects
For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program, including...
US-9,564,218 Associative memory circuit
An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the...
US-9,564,217 Semiconductor memory device having integrated DOSRAM and NOSRAM
A semiconductor memory device includes a semiconductor substrate having a main surface, at least a first dielectric layer on the main surface of the...
US-9,564,216 Stress trim and modified ISPP procedures for PCM
A memory circuit is described that includes an array of memory cells including a plurality of blocks. The circuit includes a controller including logic to...
US-9,564,215 Independent sense amplifier addressing and quota sharing in non-volatile memory
Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address...
US-9,564,214 Memory device
According to one embodiment, a memory device includes a controller; a first electrode and a second electrode connected to the controller; and a variable...
US-9,564,213 Program verify for non-volatile storage
A non-volatile storage system includes a plurality of non-volatile storage elements arranged in two dimensional or three dimensional structures. The system...
US-9,564,212 Solid-state memory corruption mitigation
Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. Certain embodiments provide a non-volatile solid-state...
US-9,564,211 Memory chip and layout design for manufacturing same
A static random access memory (SRAM) chip including a plurality of SRAM cells and a plurality of cell current tracking cells. Each of the SRAM cells include a...
US-9,564,210 Aging sensor for a static random access memory (SRAM)
A static random access memory (SRAM) includes a first bitcell and a second bitcell. The first bitcell includes an aging transistor and the second bitcell...
US-9,564,209 Non-volatile static random access memory using a 7T1R cell with initialization and pulse overwrite
A non-volatile SRAM cell comprises a first inverter, a second inverter, a first access transistor, a second access transistor, and a variable resistive element....
US-9,564,208 Low power radiation hardened memory cell
The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and an...
US-9,564,207 Semiconductor memory device, semiconductor memory system and method for controlling self refresh cycle thereof
A semiconductor memory device which performs a refresh operation. The semiconductor memory device may include an information detection unit suitable for...
US-9,564,206 Semiconductor device
Embodiments of the present invention relate to a latch circuit (L20) which latches a data mask signal (DM) in response to a one-shot signal (NS), and changes...
US-9,564,205 Memory apparatus and method for accessing memory
A memory apparatus and a memory accessing method are provided. The memory accessing method includes: calculating an accessed times of each of a plurality of...
US-9,564,204 Multi-chip package and operating method thereof
A multi-chip package includes a plurality of semiconductor devices each having an address which is designated based on unique values corresponding to the...
US-9,564,203 Semiconductor device, adjustment method thereof and data processing system
A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a...
US-9,564,202 Increased refresh interval and energy efficiency in a DRAM
Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy...
US-9,564,201 Method, apparatus and system for responding to a row hammer event
Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the...
US-9,564,200 Pillar-type field effect transistor having low leakage current
A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes: a semiconductor body, source and...
US-9,564,199 Methods of reading and writing data in a thyristor random access memory
A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.
US-9,564,198 Six-transistor SRAM semiconductor structures and methods of fabrication
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can...
US-9,564,197 Ferromagnetic device providing high domain wall velocities
The invention is directed to a method of manufacturing a ferromagnetic device (10), having an elongated structure extending along a longitudinal direction (11),...
US-9,564,196 Semiconductor memory device and data writing method using a checkerboard pattern utilizing existing data supply...
To provide a semiconductor memory device capable of writing a checkerboard pattern for interference and investigation by three writings regardless of the...
US-9,564,195 Address comparator circuit for generating transmission control signal, memory device and memory system...
An address comparator circuit includes a first determination unit suitable for activating a first control signal when a first address corresponding to a...
US-9,564,194 Input apparatus and semiconductor memory apparatus having the input apparatus
An input apparatus of a semiconductor memory may be provided. The input apparatus may include a first storage circuit configured to receive at least a portion...
US-9,564,193 Circuit to generate a sense amplifier enable signal
A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a...
US-9,564,192 Memory controller for strobe-based memory systems
An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe...
US-9,564,191 Signal compensation circuit and semiconductor apparatus using the same
A signal compensation circuit includes a first path configured to cause a source signal to pass therethrough and be outputted as a first signal; a delay block...
US-9,564,190 Semiconductor memory device with a delay locked loop circuit and a method for controlling an operation thereof
An operation control method of a semiconductor memory device includes executing a Delay Locked Loop (DLL) locking in response to a DLL reset signal and...
US-9,564,189 Memory system including semiconductor memory device and program method thereof
A method of programming a memory system includes: reading a target page included in a selected memory block in response to a program request when at least one...
US-9,564,188 Current-mode sense amplifier and reference current circuitry
An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input...
US-9,564,187 Predicting saturation in a shift operation
Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction,...
US-9,564,186 Method and apparatus for memory access
Aspects of the disclosure provide an integrated circuit that includes a first memory controller, a second memory controller and at least a functional circuit...
US-9,564,185 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a memory including a memory cell array, and an input/output pin configured to transfer data,...
US-9,564,184 Sense amplifier for single-ended sensing
A single ended line sense amplifier having an input coupled to a single ended line having a near end and a far end device comprises a plurality of nFET stacks...
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