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Patent # Description
US-9,563,578 System and method for logical deletion of stored data objects
Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation...
US-9,563,577 Memory tamper detection
A method and system for detecting tampering of authenticated memory blocks that are accessible by an untrusted host processor. by (1) periodically...
US-9,563,576 Area-limited software utility
Computers and networks are configured to operate according to alternative protocols for using software applications, depending on geographic location. In one...
US-9,563,575 Least recently used mechanism for cache line eviction from a cache memory
A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache...
US-9,563,574 Storage control device and method of controlling storage control device
To improve response performance of a storage control device. A storage control device 1 connected to a host computer 2 includes: a communication unit 1A that...
US-9,563,573 Precharge disable using predecoded address
A memory can be a sum addressed memory (SAM) that receives, for each read access, two address values (e.g. a base address and an offset) having a sum that...
US-9,563,572 Migrating buffer for direct memory access in a computer system
A computer-implemented method for migrating a buffer used for direct memory access (DMA) may include receiving a request to perform a DMA data transfer between...
US-9,563,571 Intelligent GPU memory pre-fetching and GPU translation lookaside buffer management
A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device performs...
US-9,563,570 System and methods exchanging data between processors through concurrent shared memory
A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a...
US-9,563,569 Memory transformation in virtual machine live migration
Systems and methods for lazy memory transformation in virtual machine live migration. An example method may comprise: receiving, by a computer system, a...
US-9,563,568 Hierarchical cache structure and handling thereof
A hierarchical cache structure includes at least one real indexed higher level cache with a directory and a unified cache array for data and instructions, and...
US-9,563,567 Selective cache way-group power down
A method and apparatus for selectively powering down a portion of a cache memory includes determining a power down condition dependent upon a number of accesses...
US-9,563,566 Device and method for integrated data management for nonvolatile buffer cache and nonvolatile storage
An integrated nonvolatile memory control subsystem and method are disclosed. The integrated nonvolatile memory control subsystem includes a nonvolatile buffer...
US-9,563,565 Apparatuses and methods for providing data from a buffer
Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit....
US-9,563,564 Cache allocation with code and data prioritization
Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to...
US-9,563,563 Multi-stage translation of prefetch requests
A device for multi-stage translation of prefetch requests includes a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests...
US-9,563,562 Page crossing prefetches
Prefetching is permitted to cross from one physical memory page to another. More specifically, if a stream of access requests contains virtual addresses that...
US-9,563,561 Initiation of cache flushes and invalidations on graphics processors
Methods and systems may provide for receiving, at a graphics processor, a workload from a host processor and using a kernel on the graphics processor to issue a...
US-9,563,560 Adaptive tuning of snoops
A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller...
US-9,563,559 Dynamic prioritization of cache access
Some embodiments of the inventive subject matter are directed to operations that include determining that an access request to a computer memory results in a...
US-9,563,558 Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
A technique for operating a cache memory of a data processing system includes creating respective pollution vectors to track which of multiple concurrent...
US-9,563,557 Instruction and logic for flush-on-fail operation
A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to...
US-9,563,556 Techniques for storing data and tags in different memory arrays
A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a...
US-9,563,555 Systems and methods for storage allocation
Resources of an address space are managed in dynamically sized ranges, extents, sets, and/or blocks. The address space may be divided into regions, each...
US-9,563,554 Persistent content in nonvolatile memory
Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations....
US-9,563,553 Data storing method and embedded system
A method for writing update data into a flash memory module to replace original data is provided. The flash memory module includes at least one block including...
US-9,563,552 Storage control device and storage control method
A storage control device that controls a solid state drive group including two or more solid state drives sharing data storage includes a detector that detects...
US-9,563,551 Data storage device and data fetching method for flash memory
A data storage device is provided. The data storage device, coupled to a host, includes: a flash memory; and a controller, configured to control accessing of...
US-9,563,550 Flash storage device and control method for flash memory
A FLASH memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write...
US-9,563,549 Data storage device, user device and data write method
Disclosed is an address mapping method for a data storage device using a hybrid mapping scheme. The address mapping method determines whether write data...
US-9,563,548 Error injection and error counting during memory scrubbing operations
Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or...
US-9,563,547 Testing optimized binary modules
Various embodiments test an optimized binary module. In one embodiment, a region in a set of original binary code of an original binary module in which branch...
US-9,563,546 Instrumentation system and method for testing software
One or more test controls within code under test are enabled and then executing the code under test is executed. When enabled, the test control will interact...
US-9,563,545 Autonomous propagation of system updates
A method, system, and/or computer program product propagates system upgrades to peer computers in a peer community. A peer community is defined by identifying...
US-9,563,544 Framework for automated testing of mobile apps
A framework for the automated testing of mobile applications is disclosed. A mobile application to be operated on a mobile device is built based on a source...
US-9,563,543 Test framework extension for testing logic on a modeled user interface
A testing framework extension may be provided. An application comprising a form may be created within a modeling framework. A variable associated with the form...
US-9,563,542 Identifying, quantifying, and eliminating wasted resources in software testing due to unavailability of a...
A system, method, and computer program product are provided for identifying, quantifying, and reducing wasted resources in software testing. In use, a first...
US-9,563,541 Software defect detection identifying location of diverging paths
Embodiments detect differences between software systems by comparing statements collected therefrom in an order of execution. Highlighting point(s) of...
US-9,563,540 Automated defect positioning based on historical data
Disclosed herein are a method and a system for software defect positioning. The system collects at least one type of information with respect to the defect and...
US-9,563,539 Breakpoint continuation for stream computing
A first stream operator in a stream computing application receives and processes a first stream of tuples. The processing at the first stream operator is paused...
US-9,563,538 Code path tracking
Methods, systems, and products are provided for code path tracking. Embodiments include identifying an instrumented trace point in software code to be path...
US-9,563,537 Breakpoint for predicted tuple processing time in a streaming environment
A stream of tuples is received to be processed by processing elements operating on one or more computer processors with each processing element having one or...
US-9,563,536 Performance neutral isolation of runtime discrepancies in binary code
Without using a high-level programming language source code, a set of sync points is identified in an initial binary code. The initial binary code is executed...
US-9,563,535 Intermediate representation construction for static analysis
The analysis of an intermediate representation of source or program code. An initial version of an initial representation of the source or program code is...
US-9,563,534 Debugger display of vector register contents after compiler optimizations for vector instructions
An optimizing compiler includes a vector optimization mechanism that optimizes vector instructions by eliminating one or more vector element reverse operations....
US-9,563,533 Maintaining coherent synchronization between data streams on detection of overflow
Trace data streams are generated for tracing target processor activity. Various trace data streams are synchronized using markers called sync points. The sync...
US-9,563,532 Allocation of tasks in large scale computing systems
Aspects of the invention may be used to allocate tasks among computing machines in large scale computing systems. In one aspect, the method includes executing a...
US-9,563,531 Storage of mass data for monitoring
Disclosed are various in various embodiments are systems and methods providing for storage of mass data such as metrics. A plurality of data models are...
US-9,563,530 Device state estimation apparatus, device power consumption estimation apparatus, and program
According to one embodiment, a device state estimation apparatus includes a detector and an operating state estimator. The detector detects devices in the ON...
US-9,563,529 Selective monitoring of archive and backup storage
Systems and methods for providing information security in a network environment. The method includes receiving a user selection of a data section recorded on a...
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