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Patent # Description
US-9,653,569 Compound semiconductor device and manufacturing method thereof
A compound semiconductor stacked structure is constituted by including: a buffer layer; an n-type conductive region that is formed at one portion of the buffer...
US-9,653,562 Nonvolatile memory device and method for manufacturing the same
A nonvolatile memory device includes a pipe gate electrode layer formed over a substrate; a plurality of conductive layers stacked over the pipe gate electrode...
US-9,653,557 Semiconductor device
A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region having a second conductivity type, a...
US-9,653,552 Body-tied, strained-channel multi-gate device and methods
A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor...
US-9,653,551 Field effect transistors including fin structures with different doped regions and semiconductor devices...
Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin...
US-9,653,550 MOSFET structure and manufacturing method thereof
A MOSFET structure and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100); b. forming a silicon germanium...
US-9,653,537 Controlling threshold voltage in nanosheet transistors
Embodiments are directed to a method of forming a semiconductor device and resulting structures for controlling a threshold voltage on a nanosheet-based...
US-9,653,528 Display apparatus and electronic apparatus
Disclosed herein is a display apparatus, including: a plurality of subpixels disposed adjacent each other and forming one pixel which forms a unit for formation...
US-9,653,524 Organic light emitting display apparatus
An organic light emitting display apparatus includes: a first pixel electrode and a second pixel electrode on a substrate and spaced apart from each other, each...
US-9,653,518 Light-emitting display device and method of manufacturing the same
A light-emitting display device and a method of manufacturing the same including preparing a substrate such that the substrate includes a pixel area and a seal...
US-9,653,515 Semiconductor light emitting device and semiconductor light emitting apparatus including the same
A semiconductor light emitting device includes a substrate; a light emitting structure and a Zener diode structure disposed to be spaced apart from each other...
US-9,653,513 CMOS image sensor and a method of forming the same
A complementary metal-oxide-semiconductor (CMOS) image sensor includes an implant region of a second type formed in a crystalline layer of a first type. A...
US-9,653,505 Method for fabricating photo detector having sensor element array and photo conversion element
A photo detector and a method for fabricating the same are provided. The photo detector includes a first substrate and a photo conversion element. The first...
US-9,653,501 Image sensor including color filter and method of manufacturing the image sensor
An image sensor including a color filter and a method of manufacturing the image sensor are provided. The image sensor includes a light-sensing layer configured...
US-9,653,499 Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus
A solid-state imaging device including an imaging area where a plurality of unit pixels are disposed to capture a color image, wherein each of the unit pixels...
US-9,653,494 Array substrate, display panel and display apparatus
A thin-film transistor (TFT) array substrate is provided. The thin-film transistor (TFT) array substrate comprises a substrate having at least a display region;...
US-9,653,492 Array substrate, manufacturing method of array substrate and display device
Embodiments of the disclosure provide an array substrate, a manufacturing method of the array substrate and a display device. The array substrate includes a...
US-9,653,484 Array substrate and manufacturing method thereof, display device, thin-film transistor (TFT) and manufacturing...
An array substrate and a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof. The array substrate...
US-9,653,482 Display panel and display device
A display panel comprises a TFT substrate and a display medium layer. The display medium layer is disposed on the TFT substrate. The TFT substrate comprises a...
US-9,653,475 Semiconductor device and method of manufacturing the same
According to one embodiment, a method of manufacturing a semiconductor device includes: forming a first film including a conductive material above a...
US-9,653,473 Semiconductor device and method of manufacturing the same
A semiconductor device, including: interlayer insulating patterns and conductive patterns alternately stacked on a substrate; a channel structure passing...
US-9,653,470 Individually read-accessible twin memory cells
The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and...
US-9,653,466 FinFET device and method of making the same
A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks...
US-9,653,463 Semiconductor device with different fin pitches
A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second...
US-9,653,460 Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is...
US-9,653,456 MIM capacitor formation in RMG module
A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a...
US-9,653,453 Electrostatic discharge protection device
An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a...
US-9,653,450 Electrostatic discharge protection semiconductor device
An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate...
US-9,653,446 Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including...
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells...
US-9,653,439 Three dimensional structures within mold compound
A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the...
US-9,653,438 Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof
An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer...
US-9,653,427 Integrated circuit package with probe pad structure
A package includes a substrate, the substrate having a first side and a second side, the second side being opposite the first side, and a stack of dies on a...
US-9,653,422 Chip package and method for forming the same
A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto...
US-9,653,415 Semiconductor device packages and method of making the same
The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a semiconductor device, a plurality of...
US-9,653,412 Method of manufacturing semiconductor device
On a first wafer surface of a semiconductor wafer, a projection-depression shape is formed. On the first wafer surface, a resin member is so formed to have a...
US-9,653,408 High-frequency package
A high-frequency package comprises a die; a plurality of leads; and a die pad; wherein a surface of the die pad is lower than top surfaces of the plurality of...
US-9,653,405 Chip arrangement and a method of manufacturing a chip arrangement
In various embodiments, a chip arrangement may be provided. The chip arrangement may include a metallic carrier. The chip arrangement may also include at least...
US-9,653,403 Structure and process for W contacts
Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and processes...
US-9,653,402 Semiconductor device and method for fabricating the same
A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a...
US-9,653,401 Method for forming buried conductive line and structure of buried conductive line
A method for forming a buried conductive line is described. A substrate having a trench therein and a contact area thereon is provided, wherein the trench has...
US-9,653,399 Middle-of-line integration methods and semiconductor devices
An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local...
US-9,653,396 Semiconductor device and method of manufacturing the same
A coil CL1 is formed on a semiconductor substrate SB via a first insulation film, a second insulation film is formed so as to cover the first insulation film...
US-9,653,395 Hybrid subtractive etch/metal fill process for fabricating interconnects
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form...
US-9,653,386 Compact multi-die power semiconductor package
One disclosed implementation is a power semiconductor package including a sync transistor having a drain on its top surface and a source and a gate on its...
US-9,653,385 Lead frame
A lead frame has a metal base, a silver-plated layer, and a silver oxide layer. The silver-plated layer is formed between the metal base and the silver oxide...
US-9,653,383 Semiconductor device with thick bottom metal and preparation method thereof
A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal...
US-9,653,372 Method for fabricating fan-out wafer level package and fan-out wafer level package fabricated thereby
A method for fabricating a fan-out wafer level package includes disposing a first semiconductor chip on a dummy substrate, forming a mold substrate on the first...
US-9,653,370 Systems and methods for embedding devices in printed circuit board structures
Embodiments relate to active devices embedded within printed circuit boards (PCBs). In embodiments, the active devices can comprise at least one die, such as a...
US-9,653,367 Methods including a processing of wafers and spin coating tool
A method includes performing a spin coating process. In the spin coating process, a first fluid is dispensed to a surface of a wafer. The method further...
US-9,653,366 Method of dividing wafer
Disclosed herein is a method of dividing a wafer including an exposed area incising step of lowering a cutting blade to a preset lowered position for fully...
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