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Patent # Description
US-9,679,998 Bi-directional punch-through semiconductor device and manufacturing method thereof
In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first...
US-9,679,997 Semiconductor device with suppressed two-step on phenomenon
A semiconductor device includes an IGBT region with a bottom-body region on a front surface side of an IGBT drift region, an IGBT barrier region on a front...
US-9,679,996 Semiconductor device having buried region beneath electrode and method to form the same
A semiconductor device and a process to form the same are disclosed. The semiconductor device includes a support, an active semiconductor stack including a...
US-9,679,995 Method for manufacturing thin film transistor and pixel unit thereof
The present invention is suitable to the field of electronic technology, and provides a method of manufacturing a thin film transistor and a pixel unit thereof,...
US-9,679,993 Fin end spacer for preventing merger of raised active regions
After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a...
US-9,679,985 Devices and methods of improving device performance through gate cut last process
Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for...
US-9,679,982 Semiconductor device and method of manufacturing the same
According to a method of manufacturing a semiconductor device, hard mask lines are formed in parallel in a substrate and the substrate between the hard mask...
US-9,679,976 Semiconductor device and method of manufacturing the same
According to one embodiment, a semiconductor device includes a semiconductor substrate in which a recess is provided on a back surface thereof, and a shape of...
US-9,679,972 Thin strain relaxed buffers with multilayer film stacks
A semiconductor structure can include a substrate and a substrate layer. The substrate can be formed of silicon and the substrate layer can be formed of silicon...
US-9,679,971 Semiconductor device
A semiconductor device of an embodiment includes an n-type SiC region, a metal layer, and a conductive layer provided between the n-type SiC region and the...
US-9,679,969 Semiconductor device including epitaxially formed buried channel region
A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region...
US-9,679,967 Contact resistance reduction by III-V Ga deficient surface
A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate....
US-9,679,966 Electronic device containing nanowire(s), equipped with a transition metal buffer layer, process for growing at...
The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said...
US-9,679,965 Semiconductor device having a gate all around structure and a method for fabricating the same
A semiconductor device includes a wire pattern spaced apart from a substrate and extended in a first direction, a gate electrode disposed around a circumference...
US-9,679,964 Semiconductor constructions having peripheral regions with spaced apart mesas
Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy...
US-9,679,963 Semiconductor structure and a method for processing a carrier
According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed...
US-9,679,962 FinFET and method of manufacturing the same
There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming...
US-9,679,961 Transistor with wurtzite channel
A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is...
US-9,679,959 Capacitor and contact structures, and formation processes thereof
Capacitor and contact structures are provided, as well as methods for forming the capacitor and contact structures. The methods include, for instance, providing...
US-9,679,957 Organic light-emitting display apparatus and method of manufacturing the same
An organic light-emitting display apparatus includes a substrate including a display area and a non-display area disposed on one side of the display area, a...
US-9,679,956 Organic light-emitting diode display with bottom shields
A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of...
US-9,679,955 Light emitting device
A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture...
US-9,679,950 Organic el display device
An organic EL display device includes a lower electrode that is provided at each pixel, a bank that surrounds an outer circumference of the lower electrode and...
US-9,679,949 Organic light emitting display device
An organic light emitting display device is disclosed. The organic light emitting display device includes a first sub-pixel that includes a first emission...
US-9,679,946 3-D planes memory device
The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for...
US-9,679,935 Image sensors
An image sensor may include a device isolation structure defining a plurality of pixel regions in a substrate and a photoelectric conversion element formed in...
US-9,679,933 Image sensors and methods of forming the same
An image sensor is provided. The image sensor includes a red (R) pixel, a green (G) pixel, a blue (B) pixel and an infrared (IR) pixel, and R, G and B filters...
US-9,679,930 Imaging apparatus and electronic apparatus
An imaging apparatus includes: an interposer on which an image sensor including a light reception section is disposed; a translucent member that is provided on...
US-9,679,927 Liquid crystal display with pixel transistors having different channel widths
A liquid crystal display includes a first pixel and a second pixel that extend in a data line direction. The first and second pixels are connected to a same...
US-9,679,915 Integrated circuit with well and substrate contacts
An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The...
US-9,679,913 Memory structure and method for manufacturing the same
A memory structure includes a 3D array of memory cells, a plurality of first conductive lines disposed on the 3D array, a plurality of second conductive lines...
US-9,679,907 Three-dimensional memory device with charge-trapping-free gate dielectric for top select gate electrode and...
A portion of a charge trapping layer adjacent to a select drain gate electrode can be removed employing a differential-rate etch process that provides an...
US-9,679,901 Semiconductor device and manufacturing method thereof
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of active areas, and an...
US-9,679,898 Semiconductor device having metal gate
A semiconductor device having metal gate includes a first metal gate structure and a second metal gate structure disposed in a first device region and in a...
US-9,679,892 Method of manufacturing a reverse blocking semiconductor device
A reverse blocking semiconductor device is manufactured by introducing impurities of a first conductivity type into a semiconductor substrate of the first...
US-9,679,875 Reduced volume interconnect for three-dimensional chip stack
A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive...
US-9,679,874 Semiconductor package and semiconductor device including the same
A semiconductor device includes a substrate, a first semiconductor package disposed on the substrate, and a second semiconductor package spaced apart from the...
US-9,679,872 Connection structure for semiconductor package having plural vias located within projection of conductive unit
A connection structure is provided. The connection structure comprises a conductive unit, a solder bump, a first insulating layer, a second insulating layer, a...
US-9,679,867 Semiconductor device having a low-adhesive bond substrate pair
A semiconductor device includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a...
US-9,679,865 Substrate for semiconductor package and semiconductor package having the same
A semiconductor package includes a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring...
US-9,679,860 Bump-equipped electronic component and method for manufacturing bump-equipped electronic component
A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate...
US-9,679,857 Semiconductor device and method including an intertial mass element
Disclosed is a semiconductor device comprising a stack of patterned metal layers separated by dielectric layers, the stack comprising a first conductive support...
US-9,679,856 System and method for a microfabricated fracture test structure
According to an embodiment, a micro-fabricated test structure includes a structure mechanically coupled between two rigid anchors and disposed above a...
US-9,679,855 Polymer crack stop seal ring structure in wafer level package
Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, that is configured with trenches that are dry-etched into a...
US-9,679,854 Reconfigurable repeater system
The present disclosure is directed to a reconfigurable repeater system. A system may comprise a PCB to which devices are coupled. At least one communication...
US-9,679,853 Package-on-package type package including integrated circuit devices and associated passive components on...
A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a...
US-9,679,852 Semiconductor constructions
Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the...
US-9,679,851 Graphene wiring structure and manufacturing method thereof
A graphene wring structure of an embodiment includes multilayer graphene, a first interlayer compound existing in an interlayer space of the multilayer...
US-9,679,850 Method of fabricating semiconductor structure
A semiconductor structure having tapered damascene aperture is disclosed. The semiconductor structure including an etching stop layer over an inter-layer...
US-9,679,849 3D NAND array with sides having undulating shapes
Area overhead is reduced between adjacent blocks of a 3D vertical channel memory device. In various embodiments, vertically oriented pillars that intersect...
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