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Patent # Description
US-9,679,848 Interconnect structure for semiconductor devices
An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a...
US-9,679,845 Necked interconnect fuse structure for integrated circuits
Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse...
US-9,679,844 Manufacturing a damascene thin-film resistor
In some embodiments of the present disclosure, a method for manufacturing a thin film resistor after completing a copper chemical mechanical polishing (CMP)...
US-9,679,842 Semiconductor package assembly
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor...
US-9,679,835 Method of manufacturing resin-encapsulated semiconductor device, and lead frame
A resin-encapsulated semiconductor device comprises a semiconductor chip mounted on a die pad. A plurality of leads each having an inner lead and an outer lead...
US-9,679,831 Tape chip on lead using paste die attach material
According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a...
US-9,679,828 System-on-chip electronic device with aperture fed nanofilm antenna
An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and...
US-9,679,827 3D VLSI interconnection network with microfluidic cooling, photonics and parallel processing architecture
A three-dimensional VLSI integrated circuit apparatus is disclosed having a plurality of VLSI layers. A first VLSI layer includes a first silicon sublayer...
US-9,679,826 Method for fabricating semiconductor package with stator set formed by circuits
A semiconductor package is provided, including a substrate having a top surface, a bottom surface opposing the top surface, a via communicating the top surface...
US-9,679,825 Array substrate for display device and manufacturing method thereof
The present disclosure provides an array substrate for a display device and a manufacturing method thereof. A transparent electrode pattern (ITO) may be formed...
US-9,679,824 Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in Fo-WLCSP
A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads...
US-9,679,823 Metric for recognizing correct library spectrum
A method of controlling polishing of a substrate is described. A controller stores a library having a plurality of reference spectra. The controller polishes a...
US-9,679,822 Method for monitoring epitaxial growth geometry shift
A method of monitoring an epitaxial growth geometry shift is disclosed. First, second and third trenches are formed on a semiconductor wafer. An epitaxial layer...
US-9,679,821 Methods of revising overlay correction data
Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data,...
US-9,679,820 Evaluation method of device wafer
An evaluation method of a device wafer on which plural devices are formed on a front surface and inside which a gettering layer is formed is provided. In the...
US-9,679,819 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region;...
US-9,679,818 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes...
US-9,679,817 Semiconductor structures and methods of forming the same
A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion...
US-9,679,816 Method for fabricating semiconductor device
A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating...
US-9,679,815 Semiconductor device and method of fabricating the same
A semiconductor device fabrication method includes sequentially forming a hard mask layer and a sacrificial layer on a substrate, forming an upper mandrel which...
US-9,679,814 Epitaxial lift off stack having a pre-curved handle and methods thereof
Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one...
US-9,679,813 Semiconductor structure and process for forming plug including layer with pulled back sidewall part
A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed...
US-9,679,812 Semiconductor device with self-aligned contact
Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a...
US-9,679,810 Integrated circuit having improved electromigration performance and method of forming same
An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a...
US-9,679,808 Selective formation of metallic films on metallic surfaces
Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic...
US-9,679,805 Self-aligned back end of line cut
Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal...
US-9,679,801 Dual molded stack TSV package
Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a...
US-9,679,799 Process for fabricating a semiconductor-on-insulator substrate
The present disclosure relates to a process for fabricating a plurality of semiconductor-on-insulator structures, the insulator being a layer of silicon dioxide...
US-9,679,798 Substrate conveyance apparatus and substrate peeling system
Disclosed is a substrate conveyance apparatus capable of suppressing a substrate from being damaged. The substrate conveyance apparatus includes a plurality of...
US-9,679,797 Dicing-tape integrated film for backside of semiconductor and method of manufacturing semiconductor device
The present invention is to provide a dicing-tape integrated film for the backside of a semiconductor that is capable of suppressing the transfer of the...
US-9,679,796 Anodized metal on carrier wafer
A method for processing a semiconductor wafer where an electrostatic layer is located on a surface of a handling wafer is used so the surface of the handling...
US-9,679,795 Article storage facility
An article storage facility is provided which is relatively simple in structure and in which it is easier to perform maintenance work of apparatus provided to...
US-9,679,794 Spacer, spacer transferring method, processing method and processing apparatus
According to an embodiment of present disclosure, a spacer is provided. The spacer includes at least a protrusion formed to protrude from an outer periphery of...
US-9,679,793 Optical monitoring system for coating processes
The invention concerns an optical monitoring system for the measurement of layer thicknesses of thin coatings applied in a vacuum, particularly on moving...
US-9,679,792 Temperature control system for electrostatic chucks and electrostatic chuck for same
A temperature control system, a wafer chuck, a thermal module for use with the chuck, and an apparatus for use in semiconductor manufacture are disclosed...
US-9,679,791 Heater elements with enhanced cooling
A heater assembly with enhanced cooling pursuant to various embodiments described herein makes use of fluidic flow in the insulation or in the space used for...
US-9,679,790 Singulation apparatus and method
A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an...
US-9,679,789 Wafer processing apparatus
A wafer in which a modified layer is internally formed along planned dividing lines is placed on a placement table and a water tank allows the wafer placed on...
US-9,679,788 Apparatus and method for treating substrate
Provided are an apparatus and method for treating a substrate, and more particularly, to an apparatus and method for treating a substrate using a supercritical...
US-9,679,787 Spin treatment apparatus
A spin treatment apparatus includes an annular liquid receiver, an annular cup body and an annular partitioning member. The annular liquid receiver surrounds a...
US-9,679,786 Packaging module of power converting circuit and method for manufacturing the same
The disclosure discloses a packaging module of a power converting circuit and a method for manufacturing the same. The packaging module of the power converting...
US-9,679,785 Semiconductor device and method of encapsulating semiconductor die
A semiconductor device has a semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor die. An insulating layer is formed over an...
US-9,679,784 Wafer-level packaged optical subassembly and transceiver module having same
A wafer-level packaged optical subassembly includes: a substrate element, the substrate element including a top layer and a base layer being bonded with the top...
US-9,679,783 Molding wafer chamber
A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired...
US-9,679,780 Polysilicon residue removal in nanosheet MOSFETs
A method is presented for forming a semiconductor device. The method includes depositing a sacrificial layer on a fin structure formed on a substrate and then...
US-9,679,768 Method for removing hydrogen from oxide semiconductor layer having insulating layer containing halogen element...
An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. An impurity such as hydrogen or...
US-9,679,766 Method for vertical and lateral control of III-N polarity
Disclosed herein is a method of: depositing a patterned mask layer on an N-polar GaN epitaxial layer of a sapphire, silicon, or silicon carbide substrate;...
US-9,679,765 Method of fabricating rare-earth doped piezoelectric material with various amounts of dopants and a selected...
A method of fabricating a rare-earth element doped piezoelectric material having a first component, a second component and the rare-earth element. The method...
US-9,679,764 Semiconductor device structures comprising polycrystalline CVD diamond with improved near-substrate thermal...
Disclosed is a semiconductor device structure including a III-V compound semiconductor material layer, a polycrystalline CVD diamond material layer, and an...
US-9,679,763 Silicon-on-insulator fin field-effect transistor device formed on a bulk substrate
A method for manufacturing a semiconductor device comprises forming a first diffusion stop layer on a bulk semiconductor substrate, forming a doped...
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