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| Patent # | Description |
|---|---|
| US-9,698,380 |
Electroluminescence display device with a protective layer and fabrication
method thereof Embodiments of the disclosure disclose an electroluminescence display device and a fabrication method thereof. The device comprises a color filter substrate.... |
| US-9,698,368 |
Display module with white light A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first... |
| US-9,698,364 |
Organic thin film transistor, preparing method thereof, and preparation
equipment An organic thin film transistor, a preparing method thereof, and a preparation equipment. The preparation equipment of an organic thin film transistor... |
| US-9,698,363 |
RF-transistors with self-aligned point contacts A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also... |
| US-9,698,348 |
Polymers based on fused diketopyrrolopyrroles The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (I), wherein Y is a group of formula (II); and their use as... |
| US-9,698,342 |
Contact layer for magnetic tunnel junction element and manufacturing
method thereof According to one embodiment, a semiconductor memory device includes a magnetic tunnel junction (MTJ) element includes a first magnetic layer, a second magnetic... |
| US-9,698,326 |
Optoelectronic semiconductor component An optoelectronic semiconductor component including an optoelectronic semiconductor chip having a first surface, wherein the first surface is a radiation... |
| US-9,698,322 |
Lighting device and method of making lighting device A lighting device comprises a solid state light emitter on a circuit board, and an optic held in place relative to the first circuit board, a voltage drop... |
| US-9,698,318 |
Light emitting device A light emitting device includes a base member, a light emitting element, and a sealing member. The substrate includes a wiring portion. The element is arranged... |
| US-9,698,316 |
Method for producing a laterally structured phosphor layer and
optoelectronic component comprising such a... A method for producing a laterally structured phosphor layer and an optoelectronic component comprising such a phosphor layer are disclosed. In an embodiment... |
| US-9,698,313 |
Solid state white light emitter and display using same A light emitting assembly comprising a solid state device coupleable with a power supply constructed and arranged to power the solid state device to emit from... |
| US-9,698,299 |
Integrated circuit combination of a target integrated circuit and a
plurality of thin film photovoltaic cells... A device having a plurality of thin film photovoltaic cells (PV) formed over a passivation layer. The device comprises a plurality of thin film photovoltaic... |
| US-9,698,279 |
Thin film transistor array substrate, organic light-emitting display
apparatus, and method of manufacturing the... Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in... |
| US-9,698,276 |
Semiconductor device, module, and electronic device Provided is an element with stable electrical characteristics or a device including plural kinds of elements with stable electrical characteristics. The... |
| US-9,698,270 |
FinFET with dual workfunction gate structure A semiconductor device includes a substrate having a fin structure, the fin structure having a height in a substantially perpendicular direction to the... |
| US-9,698,248 |
Power MOS transistor and manufacturing method therefor The present invention discloses a power Metal Oxide Semiconductor (MOS) transistor, wherein a second U-shaped trench is formed below a first U-shaped trench, so... |
| US-9,698,246 |
LDMOS device with graded body doping A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is... |
| US-9,698,240 |
Semiconductor device and formation thereof A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first... |
| US-9,698,235 |
Field-effect transistor The present invention provides a field-effect transistor having an accumulation-layer-operation type field-effect transistor that includes a semiconductor layer... |
| US-9,698,234 |
Interface layer for gate stack using O.sub.3 post treatment Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O.sub.3 post treatment. Aspects... |
| US-9,698,227 |
FinFET with trench field plate An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second... |
| US-9,698,226 |
Recess liner for silicon germanium fin formation Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon... |
| US-9,698,223 |
Memory device containing stress-tunable control gate electrodes A memory film and a semiconductor channel are formed within each memory opening that extends through a stack including an alternating plurality of insulator... |
| US-9,698,222 |
Method of fabricating semiconductor structures on dissimilar substrates Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask... |
| US-9,698,217 |
Semiconductor device A semiconductor device of trench gate type is provided that has achieved both large on-current and high off-state breakdown voltage. Around trench T and between... |
| US-9,698,201 |
High density selector-based non volatile memory cell and fabrication A high density non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a... |
| US-9,698,200 |
Magnetism-controllable dummy structures in memory device A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first... |
| US-9,698,192 |
Two-color barrier photodetector with dilute-nitride active region Embodiments described herein relate to a dual-band photodetector. The dual-band photodetector includes a barrier layer (10) disposed between two infrared... |
| US-9,698,191 |
System and method to extend near infrared spectral response for imaging
systems One innovation includes an IR sensor having an array of sensor pixels to convert light into current, each sensor pixel of the array including a photodetector... |
| US-9,698,181 |
Semiconductor detector device A semiconductor detector device comprises a layer of semiconductor material for generating charge in response to an input event and an array of pixels for... |
| US-9,698,177 |
Method for manufacturing N-type TFT The present invention provides a method for manufacturing the N-type TFT, which includes subjecting a light shielding layer to a grating like patternization... |
| US-9,698,173 |
Thin film transistor, display, and method for fabricating the same A thin film transistor (TFT) device is provided. The TFT device includes a first conductive layer including a gate electrode and a connection pad. The TFT... |
| US-9,698,160 |
Method for transferring micro devices and method for manufacturing display
panel A method for transferring micro devices is provided. The method includes the following operations: providing a carrier substrate and forming micro devices on... |
| US-9,698,151 |
Vertical memory devices A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of... |
| US-9,698,149 |
Non-volatile memory with flat cell structures and air gap isolation High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The... |
| US-9,698,134 |
Method for manufacturing a light emitted diode display A method for manufacturing a micro LED display is provided. The method includes providing a plurality of LED elements on a first substrate, transferring, using... |
| US-9,698,133 |
Method of manufacturing a multichip package structure A method of manufacturing a multichip package structure includes providing a substrate body; placing a plurality of light-emitting chips on the substrate body,... |
| US-9,698,132 |
Chip package stack up for heat dissipation A chip package stack up includes a processor chip package that has a top surface and a bottom surface, an interposer, disposed above and connected to the... |
| US-9,698,118 |
Method and apparatus for connecting packages onto printed circuit boards Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer... |
| US-9,698,115 |
Three-dimensional chip stack and method of forming the same A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection... |
| US-9,698,110 |
Semiconductor device with integrated antenna A high frequency signal can be transmitted and received in a semiconductor device. In a QFP, an antenna (frame body) is supported by three suspension leads. The... |
| US-9,698,108 |
Structures to mitigate contamination on a back side of a semiconductor
substrate Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a... |
| US-9,698,102 |
Power and ground routing of integrated circuit devices with improved IR
drop and chip performance An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first... |
| US-9,698,098 |
Anti-fuse structure and method for manufacturing the same A method for manufacturing a semiconductor device includes forming a fin extending between first and second pads on a substrate, removing a central portion of... |
| US-9,698,093 |
Universal BGA substrate A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending... |
| US-9,698,091 |
Power semiconductor device A power semiconductor device includes an insulating substrate, a semiconductor element, a case, and a wiring member. The case forms a container body having a... |
| US-9,698,083 |
Three-dimensional stack of leaded package and electronic member An electronic device comprising a package comprising an encapsulated electronic chip, at least one at least partially exposed electrically conductive carrier... |
| US-9,698,080 |
Conductor structure for three-dimensional semiconductor device A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor... |
| US-9,698,077 |
Heat conductive silicone composition based on combination of components,
heat conductive layer, and... Provided is a heat conductive silicone composition disposed between a heat generating electronic component and a member for dispersing heat, wherein the heat... |
| US-9,698,063 |
Method of testing a semiconductor-on-insulator structure and application
of said test to the fabrication of... The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of... |
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