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Patent # Description
US-9,748,377 Semiconductor device and method of manufacturing the same
A semiconductor device includes a gate structure, a source region and a drain region. The source region and the drain region are on opposite sides of the gate...
US-9,748,376 Power FET with integrated sensors and method of manufacturing
A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors...
US-9,748,375 Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact
A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each...
US-9,748,374 Semiconductor device having a field-effect structure and a nitrogen concentration profile
A semiconductor device includes a silicon semiconductor body having a main surface and a nitrogen concentration which is lower than about 2*10.sup.14 cm.sup.-3...
US-9,748,373 MISFET device
Embodiments of the present disclosure include a MISFET device. An embodiment includes a source/drain over a substrate, a first etch stop layer on the...
US-9,748,372 Semiconductor structure and method of forming the same
A method of forming a semiconductor structure includes growing a second III-V compound layer over a first III-V compound layer, wherein the second III-V...
US-9,748,370 Trench MOS semiconductor device
To prevent a malfunction of an overcurrent protection circuit without increasing an on-voltage, and to suppress a short circuit capacity, thus further reducing...
US-9,748,369 Lateral bipolar junction transistor (BJT) on a silicon-on-insulator (SOI) substrate
A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in...
US-9,748,368 Tunnel field-effect transistor (TFET) with supersteep sub-threshold swing
Technologies are generally described herein generally relate to tunnel field-effect transistor (TFETs) structures with a gate-on-germanium source (GoGeS) on...
US-9,748,367 Method for making thim film transistor
A method for making a thin film transistor includes a step of forming a semiconducting layer, a source electrode, a drain electrode, a gate electrode, and an...
US-9,748,366 Etching oxide-nitride stacks using C.sub.4F.sub.6H.sub.2
An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising...
US-9,748,365 SiGe and Si FinFET structures and methods for making the same
FinFET structures and methods for making the same. A method includes: creating a plurality of Silicon fins on a first region of a substrate, creating a...
US-9,748,364 Method for fabricating three dimensional device
A method for forming a three dimensional device. The method may include directing ions to an end surface of an extension region of a fin structure, the fin...
US-9,748,363 Semiconductor device including fin structures and manufacturing method thereof
A method for manufacturing a semiconductor device includes forming a fin structure having a top surface and side surfaces. A mask layer is disposed over the top...
US-9,748,362 High-voltage normally-off field effect transistor with channel having multiple adjacent sections
A device having a channel with multiple voltage thresholds is provided. The channel can include a first section located adjacent to a source electrode, which is...
US-9,748,361 Integrated circuits using guard rings for ESD systems, and methods for forming the integrated circuits
An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated...
US-9,748,360 Manufacturing method of semiconductor device
The present invention makes it possible to improve the reliability of a semiconductor device. In a manufacturing method of a semiconductor device according to...
US-9,748,359 Vertical transistor bottom spacer formation
A silicon layer is formed on a surface of each bottom source/drain region that is present at the footprint of a semiconductor fin. A first set of atoms...
US-9,748,358 Gap fill of metal stack in replacement gate process
A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate...
US-9,748,357 III-V MOSFET with strained channel and semi-insulating bottom barrier
Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a...
US-9,748,356 Threshold adjustment for quantum dot array devices with metal source and drain
Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the...
US-9,748,355 Method for manufacturing oxide semiconductor transistor with low-nitrogen, low-defect insulating film
The amount of nitrogen that is transferred to an oxide semiconductor film of a transistor including the oxide semiconductor film is reduced. In addition, in a...
US-9,748,354 Multi-threshold voltage structures with a lanthanum nitride film and methods of formation thereof
Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some...
US-9,748,353 Method of making a gallium nitride device
A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate;...
US-9,748,352 Multi-channel gate-all-around FET
A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional...
US-9,748,351 Process for integrated circuit fabrication including a uniform depth tungsten recess technique
Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first...
US-9,748,350 Semiconductor structure with enlarged gate electrode structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate....
US-9,748,349 Semiconductor device
A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around...
US-9,748,348 Fully-depleted SOI MOSFET with U-shaped channel
A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that...
US-9,748,347 Gate with self-aligned ledged for enhancement mode GaN transistors
An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The...
US-9,748,346 Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of...
US-9,748,345 Modification of electrical properties of topological insulators
Ion implantation or deposition can be used to modify the bulk electrical properties of topological insulators. More particularly, ion implantation or deposition...
US-9,748,344 Nitride semiconductor substrate having recesses at interface between base substrate and initial nitride
The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal...
US-9,748,343 Semiconductor device
A semiconductor device of an embodiment includes a SiC layer having a surface inclined with respect to a {000-1} face at an angle of 0.degree. to 10.degree. or...
US-9,748,342 Semiconductor device and method for manufacturing the same
A semiconductor device according to an embodiment includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC layer provided on the SiC...
US-9,748,341 Metal-oxide-semiconductor (MOS) devices with increased channel periphery
A semiconductor device includes a drift layer disposed on a substrate. The drift layer has a non-planar surface having a plurality of repeating features...
US-9,748,340 Graphene field effect transistor
Graphene FETs exhibit low power consumption and high switching rates taking advantage of the excellent mobility in graphene deposited on a rocksalt oxide (111)...
US-9,748,339 Semiconductor device and method for fabricating the same
A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereon; a first well region disposed in a portion of the...
US-9,748,338 Preventing isolation leakage in III-V devices
A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a...
US-9,748,337 Semiconductor memory device
Three directions intersecting each other are referred to as first to third directions. A semiconductor memory device according to embodiments includes a...
US-9,748,336 Semiconductor device including dual-layer source/drain region
A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a...
US-9,748,335 Method, apparatus and system for improved nanowire/nanosheet spacers
A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or...
US-9,748,334 Fabrication of nanomaterial T-gate transistors with charge transfer doping layer
A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a...
US-9,748,333 Semiconductor structure including dummy structure and semiconductor pattern structure including dummy structure
A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy...
US-9,748,332 Non-volatile semiconductor memory
A semiconductor device includes a semiconductor substrate, multiple memory cells on the semiconductor substrate arranged along a first dimension and along a...
US-9,748,331 Method for growing III-V epitaxial layers
Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor...
US-9,748,330 Semiconductor device having self-isolating bulk substrate and method therefor
In one embodiment, a semiconductor device comprises a bulk semiconductor substrate that includes a first conductivity type floating buried doped region bounded...
US-9,748,329 Trench-based power semiconductor devices with increased breakdown voltage characteristics
Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
US-9,748,328 Oxide semiconductor film
A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer,...
US-9,748,327 Pillar resistor structures for integrated circuitry
Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in...
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