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Patent # Description
US-9,748,275 Display device
To provide a display device including a flexible panel that can be handled without seriously damaging a driver circuit or a connecting portion between circuits....
US-9,748,274 Memory device comprising stacked memory cells and electronic device including the same
A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a...
US-9,748,273 Semiconductor device
A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are...
US-9,748,272 Semiconductor-on-insulator with back side strain inducing material
Embodiments of the present invention provide for the application of strain inducing layers to enhance the mobility of transistors formed on ...
US-9,748,271 Hybrid circuit including a tunnel field-effect transistor
The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel...
US-9,748,270 Tunable capacitor for FDSOI applications
The present disclosure provides in one aspect a semiconductor device including an SOI substrate with an active semiconductor layer disposed on a buried...
US-9,748,269 Fuse programmable logic circuitry with multiple transistor pillars
Transistor pillars have multiple transistor stacks of drain, source and gate rings. Layer fuses connect the rings to conductive layers surrounding the...
US-9,748,268 Semiconductor memory device
A semiconductor memory device including a first electrode layer provided on a conductive layer; a second electrode layer provided between the conductive layer...
US-9,748,267 Three dimensional NAND device with channel contacting conductive source line and method of making thereof
A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first...
US-9,748,266 Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods...
A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a...
US-9,748,265 Integrated structures comprising charge-storage regions along outer portions of vertically-extending channel...
Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include...
US-9,748,264 Semiconductor structure and manufacturing method thereof
A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a substrate, conductive layers, insulating layers, a...
US-9,748,263 Semiconductor memory device
A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, ...
US-9,748,262 Memory structure and manufacturing method of the same
A memory structure and a manufacturing method thereof are provided. The memory structure includes a bottom oxide layer, a first conductive layer on the bottom...
US-9,748,261 Method of fabricating memory device
A method of fabricating a memory device includes alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate,...
US-9,748,260 Nonvolatile semiconductor memory device and manufacturing method thereof
A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the...
US-9,748,259 Method of forming a semiconductor device structure and semiconductor device structure
The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an...
US-9,748,258 Three-dimensional semiconductor devices
A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode...
US-9,748,257 Semiconductor devices having dummy patterns and methods of fabricating the same
Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral...
US-9,748,256 Semiconductor device and method of forming the same
Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select...
US-9,748,255 Split gate memory devices and methods of manufacturing
Some embodiments of the present disclosure relate to a memory device, which includes a floating gate formed over a channel region of a substrate, and a control...
US-9,748,254 Convex shaped thin-film transistor device having elongated channel over insulating layer in a groove of a...
The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density....
US-9,748,252 Antifuse element utilizing non-planar topology
Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements...
US-9,748,251 Methods of forming semiconductor devices using semi-bidirectional patterning
Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an...
US-9,748,250 Deep trench sidewall etch stop
Embodiments of the present invention provide a structure and method for fabrication of deep trenches in semiconductor-on-insulator structures. An upper portion...
US-9,748,249 Tantalum-containing film forming compositions and vapor deposition of tantalum-containing films
Tantalum-containing film forming compositions are disclosed, along with methods of synthesizing the same, and methods of forming Tantalum-containing films on...
US-9,748,248 Semiconductor device having buried gate structure, method for manufacturing the same, memory cell having the...
A semiconductor device includes a substrate including a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned in the...
US-9,748,247 Semiconductor device
A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in...
US-9,748,246 Semiconductor integrated circuits having contacts spaced apart from active regions
First and second active regions are doped with different types of impurities, and extend in a first direction and spaced apart from each other in a second...
US-9,748,245 Multiple finFET formation with epitaxy separation
A semiconductor device including an nFET device and pFET device adjacent one another. The semiconductor device includes a shallow trench isolator (STI), a gate...
US-9,748,244 Method for manufacturing semiconductor device and semiconductor device
A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second...
US-9,748,243 Semiconductor device having contact plugs and method of forming the same
A semiconductor device including a first fin active area substantially parallel to a second fin active area, a first source/drain in the first fin active area,...
US-9,748,242 Semiconductor device
A semiconductor device is provided that includes a composite semiconductor body including a high voltage depletion-mode transistor and a low voltage...
US-9,748,241 Semiconductor device for simultaneous operation at two temperature ranges
A semiconductor device for simultaneous operation at two temperature ranges includes a substrate, a first transistor, and a second transistor. The substrate has...
US-9,748,240 Semiconductor device including a boundary of conductivity in a substrate
A device includes first and second semiconductor-regions located in a substrate which are adjacent to each other at a boundary. First contacts are located in...
US-9,748,239 Fin-double-gated junction field effect transistor
A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a...
US-9,748,238 Semiconductor device and method of manufacturing the same
A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from...
US-9,748,237 Semiconductor integrated circuit and logic circuit
Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first...
US-9,748,236 FinFET device with enlarged channel regions
A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate...
US-9,748,235 Gate stack for integrated circuit structure and method of forming same
One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a...
US-9,748,234 Semiconductor devices and methods of fabricating the same
Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of...
US-9,748,233 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a...
US-9,748,232 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region and a first drain region. The...
US-9,748,231 Semiconductor device
A semiconductor device includes: a substrate; a first active region formed in the substrate and that includes a first region that has a first width and a second...
US-9,748,230 Semiconductor apparatus having a trench Schottky barrier Schottky diode
A semiconductor apparatus having a trench Schottky barrier Schottky diode, which includes: a semiconductor volume of a first conductivity type, which...
US-9,748,229 Semiconductor device
A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n.sup.+ emitter region and...
US-9,748,228 Structure and method for cooling three-dimensional integrated circuits
A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the...
US-9,748,227 Dual-sided silicon integrated passive devices
In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface...
US-9,748,226 Decoupling capacitor
A device is disclosed that includes active areas, gates, and conductors. The active areas are disposed apart from each other. The gates are crossing over the...
US-9,748,225 Semiconductor device with power transistors coupled to diodes
The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power...
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