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Patent # Description
US-9,748,224 Heterojunction semiconductor device having integrated clamping device
In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a...
US-9,748,223 Six-transistor SRAM semiconductor structures and methods of fabrication
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can...
US-9,748,222 Fin type electrostatic discharge protection device
A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a...
US-9,748,221 Electrostatic discharge protection device and manufacturing method thereof
An electrostatic discharge (ESD) protection device includes two N-metal oxide semiconductor (NMOS) elements and a doped region. The two NMOS elements are...
US-9,748,220 Gate-bounded silicon controlled rectifier
A gate-bounded silicon controlled rectifier includes a substrate, an N-type well region, a P-type well region, a first N-type semiconductor region, a first...
US-9,748,219 Self-balanced silicon-controlled rectification device
A self-balanced silicon-controlled rectification device includes a substrate, an N-type doped well, a P-type doped well, at least one heavily doped clamping...
US-9,748,218 Method and apparatus to facilitate direct surface cooling of a chip within a 3D stack of chips using optical...
In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very...
US-9,748,217 Method of producing semiconductor device
A semiconductor device production method where separate semiconductor chips are stacked on a semiconductor substrate having a main surface on which multiple...
US-9,748,216 Apparatus and method for a component package
A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers...
US-9,748,214 Techniques for tiling arrays of pixel elements and fabricating hybridized tiles
A first substrate having an array of emitters or detectors may be joined by bump bonding with a second substrate having read-in (RIIC) or read-out (ROIC)...
US-9,748,213 Circuit device and method for the production thereof
A circuit device has a base plate, a first substrate arranged on a first outer side of the base plate, a second substrate arranged on a second outer side...
US-9,748,212 Shadow pad for post-passivation interconnect structures
Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect...
US-9,748,211 Array-type double-side light-emitting device and manufacturing method thereof and double-side display device
The present invention relates to an array-type double-side light-emitting device, a manufacturing method thereof and a double-side display device. The...
US-9,748,210 Method for transfer of semiconductor devices
A method of transferring semiconductor devices to a product substrate includes positioning a surface of the product substrate to face a first surface of a...
US-9,748,209 Light source device having multiple LED chips of different thickness
A light source device including a substrate, a plurality of first light emitting diode (LED) chips, and at least one second LED chip is provided. The substrate...
US-9,748,208 Light-emitting device
A light-emitting device includes a substrate, and a plurality of light-emitting arrays or light-emitting groups arranged on the substrate. The light-emitting...
US-9,748,207 Bonded dies with isolation
An electronic circuit structure is formed with first and second dies bonded together. A first active layer is formed in the first die, and a second active layer...
US-9,748,206 Three-dimensional stacking structure and manufacturing method thereof
A three-dimensional stacking structure and the manufacturing method(s) thereof are described. The stacking structure includes at least a bottom die, a top die...
US-9,748,205 Molding type power module
A molding type power module includes: a leadframe including a first step and a second step; a first planar power device including a first surface having...
US-9,748,204 Semiconductor device including semiconductor chips stacked over substrate
According to the present invention, a semiconductor device includes a substrate including a first surface and a second surface opposite to the first surface, a...
US-9,748,203 Integrated circuit packaging system with conductive pillars and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system including: providing a package carrier; mounting an integrated circuit to the package carrier;...
US-9,748,202 Semiconductor device
A semiconductor device includes a first circuit board having a first chip and a second chip mounted on a first base, the second chip having a greater height...
US-9,748,201 Semiconductor packages including an interposer
A semiconductor package may include a first semiconductor chip, second semiconductor chips disposed to respectively overlap with portions of the first...
US-9,748,200 Manufacturing method of wafer level package structure
A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an...
US-9,748,199 Thermal compression bonding process cooling manifold
Embodiments of a thermal compression bonding (TCB) process cooling manifold, a TCB process system, and a method for TCB using the cooling manifold are...
US-9,748,198 Hybrid bonding systems and methods for semiconductor wafers
Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a...
US-9,748,197 Methods for packaging integrated circuits
Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the...
US-9,748,196 Semiconductor package structure including die and substrate electrically connected through conductive segments
The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate,...
US-9,748,195 Adhesive for mounting flip chip for use in a method for producing a semiconductor device
The present invention aims to provide a method for producing a semiconductor device, the method being capable of achieving high reliability by suppressing...
US-9,748,194 Electronic device
An electronic device includes a mount board, first and second electronic components flip-chip mounted on a surface of the mount board with bumps interposed...
US-9,748,193 Printed circuit board and semiconductor package using the same
A printed circuit board (PCB) includes: a base substrate including a top surface including an electronic device mounting region; chip connection pads that are...
US-9,748,192 Printed circuit board having a post bump
Provided are a printed circuit board which can be used as a substrate for a package, a method of manufacturing the printed circuit board, and a semiconductor...
US-9,748,191 Semiconductor device and a method of manufacturing the same
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a...
US-9,748,190 Low cost and ultra-thin chip on wafer on substrate (CoWoS) formation
Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer,...
US-9,748,189 Multi-chip package structure and method of forming same
A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of...
US-9,748,188 Method of forming a bump on pad (BOP) bonding structure in a semiconductor packaged device
The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated...
US-9,748,187 Wafer structure and method for wafer dicing
The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding...
US-9,748,186 Semiconductor device and method for manufacturing the semiconductor device
A semiconductor device has a module structure in which a semiconductor element and a circuit layer are electrically connected to each other by a wire. A front...
US-9,748,185 Semiconductor devices with impedance matching-circuits
Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation...
US-9,748,184 Wafer level package with TSV-less interposer
A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first...
US-9,748,183 Fabrication method of semiconductor package
A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first...
US-9,748,182 Wafer processing method
Disclosed herein is a wafer processing method including a stacked member removing step of applying a laser beam having an absorption wavelength to a stacked...
US-9,748,181 Methods and apparatus for crack propagation prevention and enhanced particle removal in scribe line seals
An example apparatus includes a plurality of scribe streets arranged in rows and columns on the surface of a semiconductor wafer; and a plurality of integrated...
US-9,748,180 Through-body via liner deposition
Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an...
US-9,748,179 Package and method of manufacturing the same
The package includes: a substrate having at least one circuit layer; at least one electronic component mounted on at least one surface of the substrate; a...
US-9,748,178 Semiconductor device, solid-state imaging device, and imaging device
A semiconductor device includes a first substrate, a second substrate, a connection part, and an alignment mark. The connection part includes a first electrode...
US-9,748,177 Embedded structures for package-on-package architecture
Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer...
US-9,748,176 Pattern placement error compensation layer in via opening
A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric...
US-9,748,175 Conductive structure in semiconductor structure and method for forming the same
A method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming an organosilicon layer...
US-9,748,174 Three-dimensional memory device having multi-layer diffusion barrier stack and method of making thereof
An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating...
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