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Patent # Description
US-9,748,173 Hybrid interconnects and method of forming the same
A method for manufacturing a semiconductor device includes forming a trench in at least one dielectric layer; and forming an interconnect structure in the...
US-9,748,172 Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines
A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It...
US-9,748,171 Memory structure
A memory structure is provided. The memory structure includes a first chip. The first chip has an array region and a periphery region. The first chip includes a...
US-9,748,170 Semiconductor devices having staggered air gaps
A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns...
US-9,748,169 Treating copper interconnects
Techniques relate to treating metallic interconnects of semiconductors. A metallic interconnect is formed in a layer. A metallic cap is disposed on top of the...
US-9,748,168 Substrate with routing
A substrate having an edge; a first and second active trace, wherein the first active trace corresponds to a first signal of a differential pair and the second...
US-9,748,167 Silicon interposer, semiconductor package using the same, and fabrication method thereof
A silicon interposer includes a substrate having a frontside surface and a backside surface, a first redistribution layer (RDL) structure disposed on the...
US-9,748,166 Semiconductor devices including control and load leads of opposite directions
A device includes a carrier and a semiconductor chip arranged over a surface of the carrier. The semiconductor chip includes a control electrode and a load...
US-9,748,165 Packaging structure
A packaging structure includes a lead frame, a chip, and a packaging material. The lead frame has a pair of opposed first surface and second surface, and has a...
US-9,748,164 Semiconductor device
A lead frame of high quality which can endure direct bonding to the electrodes of a semiconductor element and a metal member, and a semiconductor device of high...
US-9,748,163 Die support for enlarging die size
A chip package, in some embodiments, comprises: a die flag; one or more die supports; and a die mounted on the die flag and on said one or more die supports, at...
US-9,748,162 Chip to wafer package with top electrodes and method of forming
A chip package and a method for forming the same are provided. The method includes: providing a first chip, wherein the first chip comprises a first surface and...
US-9,748,161 Heat dissipation device
A heat dissipation device includes a base, a fin assembly mounted on a top surface of the base, and a heat absorber arranged at a bottom surface of the base....
US-9,748,160 Semiconductor package, method of fabricating the same, and semiconductor module
A semiconductor package, a semiconductor module, a method of fabricating a semiconductor package are disclosed. The semiconductor package may include a...
US-9,748,159 Electronic device provided with an integral conductive wire and method of manufacture
An electronic device includes a supporting substrate having a front mounting face and an electrical connection network. An integrated circuit chip is mounted to...
US-9,748,158 Liquid sealing material and electronic component using same
A liquid sealing material which has excellent PCT (pressure cooker test) resistance, and an electronic component which is obtained by sealing a part to be...
US-9,748,157 Integrated circuit packaging system with joint assembly and method of manufacture thereof
An integrated circuit packaging system and method of manufacture thereof includes: a base substrate having a bottom pad; an integrated circuit device mounted on...
US-9,748,156 Semiconductor package assembly, semiconductor package and forming method thereof
A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner...
US-9,748,155 Printed circuit board
A printed wiring board includes a power supply conductor pattern arranged on one conductor layer, one ground conductor pattern arranged on the one conductor...
US-9,748,154 Wafer level fan out semiconductor device and manufacturing method thereof
A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a...
US-9,748,153 Process for making and using a semiconductor wafer containing first and second does of standard cell...
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill...
US-9,748,152 Semiconductor arrangement and formation thereof
Forming a semiconductor arrangement includes non-destructively determining a first spacer height of a first sidewall spacer adjacent a dummy gate and a second...
US-9,748,151 Method for evaluating semiconductor substrate
The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in...
US-9,748,150 Test line structure and method for performing wafer acceptance test
Test line structures on a wafer are provided. A first testing pad is formed in a scribe line of the wafer. A second testing pad is formed in the scribe line. A...
US-9,748,149 Method of manufacturing a silicon carbide semiconductor device including forming a protective film with a...
A method of manufacturing a silicon carbide semiconductor device includes ion implanting an impurity into a surface of a semiconductor substrate comprised of...
US-9,748,148 Localized stress modulation for overlay and EPE
Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion...
US-9,748,147 Method of fabricating epitaxial layer
A method of fabricating an epitaxial layer includes providing a silicon substrate. A dielectric layer covers the silicon substrate. A recess is formed in the...
US-9,748,146 Single spacer for complementary metal oxide semiconductor process flow
A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region...
US-9,748,145 Semiconductor devices with varying threshold voltage and fabrication methods thereof
Semiconductor device fabrication methods are provided which include: providing a structure with at least one region and including a dielectric layer disposed...
US-9,748,144 Method of fabricating semiconductor device
First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate,...
US-9,748,143 FinFETs with strained well regions
A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having...
US-9,748,142 FinFETs with strained well regions
A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first...
US-9,748,141 Semiconductor device and method for manufacturing the same
Provided are a semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second...
US-9,748,140 Method of manufacturing semiconductor devices
A method for use in manufacturing semiconductor devices includes providing a wafer on a support, covering a central wafer portion of the wafer, and cutting a...
US-9,748,139 Method of fabricating dual damascene structure
A substrate having thereon a first dielectric layer, a second dielectric layer, and a hard mask layer is provided. A partial via is formed in the second...
US-9,748,138 Metal layer end-cut flow
A method of patterning a metal layer is disclosed. The method includes providing a substrate and forming a material layer over the substrate. The method...
US-9,748,137 Method for void-free cobalt gap fill
Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt,...
US-9,748,136 Method for forming an electrically conductive via in a substrate
A method for forming an electrically conductive via in a substrate that includes the steps of: forming a through hole in a first substrate; bringing a first...
US-9,748,135 Substrate including selectively formed barrier layer
A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a...
US-9,748,134 Method of making interconnect structure
A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer...
US-9,748,133 Via definition scheme
A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop...
US-9,748,132 Substrate processing apparatus, method for manufacturing semiconductor device, method for processing substrates
A substrate supporting member provided in a processing chamber for processing the substrate and configured to support the substrate, has on its upper surface, a...
US-9,748,131 Low temperature adhesive resins for wafer bonding
A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an...
US-9,748,130 Wafer taping scheme
A method includes setting a first tension value of a laminating tape during a standby mode. A second tension value of the laminating tape is set during taping...
US-9,748,128 Systems and methods for wafer alignment
Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations....
US-9,748,127 Structure for fastening together resin members in substrate storing container
The upper wall is provided with a recess indented from the outside toward the inside of the container main body, and a protrusion projecting outward on the...
US-9,748,125 Continuous substrate processing system
A processing chamber having a plurality of movable substrate carriers stacked therein for continuously processing a plurality of substrates is provided. The...
US-9,748,124 Vacuum processing apparatus and operating method thereof
An operating ratio is improved in a vacuum processing apparatus to which a plurality of vacuum transfer chambers are connected through a vacuum transfer...
US-9,748,123 Pressure-controlled wafer carrier and wafer transport system
Disclosed are a wafer carrier that keeps wafers under a constant pressure, at any preset value below or above the atmospheric pressure, to prevent wafer...
US-9,748,122 Thermal processing apparatus and method of controlling the same
A control unit can select a large-number control zone model in which the number of control zones, which are independently controlled, is large, and a...
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