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Patent # Description
US-9,747,251 Video encoding and decoding using parallel processors
A method is disclosed for the decoding and encoding of a block-based video bit-stream such as MPEG2, H.264-AVC, VC1, or VP6 using a system containing one or...
US-9,747,250 Effective memory management for host objects in a runtime environment with embedded garbage-collected based...
A system for improving memory management in a hybrid programming environment where a server program receives a request to execute a script. The server program...
US-9,747,249 Methods and systems to achieve multi-tenancy in RDMA over converged Ethernet
A method for providing multi-tenancy support for RDMA in a system that includes a plurality of physical hosts. Each physical host hosts a set of data compute...
US-9,747,248 Wireless communication system
A processing system is described that includes a wireless communication interface that wirelessly communicates with one or more wireless client devices in the...
US-9,747,247 Serial peripheral interface and method for data transmission
A serial peripheral interface of an integrated circuit includes: a first transfer pin for receiving an instruction and an address; and a clock pin for inputting...
US-9,747,246 Electronic device for communicating between a microcontroller unit (MCU) and a host processor and related methods
An electronic device may include system and serial peripheral interface (SPI) clocks, and a host interface each switchable between active and inactive states, a...
US-9,747,245 Method, apparatus and system for integrating devices in a root complex
In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at...
US-9,747,244 Clockless virtual GPIO
A virtual GPIO architecture for an integrated circuit is provided that both serializesvirtual GPIO signals and deserializes virtual GPIO signals without the...
US-9,747,243 Electronic equipment for the replication of ports and the routing of digital signals
The present disclosure relates to a piece of electronic equipment for the replication of ports and the routing of digital signals, intended for secure...
US-9,747,242 Methods and apparatuses for providing data received by a plurality of state machine engines
An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine...
US-9,747,241 Address caching in switches
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing an address in a memory of a switch. One of the...
US-9,747,240 Dynamic connection of PCIe devices and functions to an array of hosts
Systems and methods for connecting a device to one of a plurality of processing hosts. A virtual interface card (VIC) adapter learns the number and location of...
US-9,747,239 Transaction filter for on-chip communications network
A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit...
US-9,747,238 Computer processor employing split crossbar circuit for operand routing and slot-based organization of...
A computer processor including a plurality of functional units that performs operations that produce result operands at different characteristic latencies over...
US-9,747,237 Methods and apparatus for reliable detection and enumeration of devices
Methods and apparatus for reliable detection and enumeration of devices. In one embodiment, the controller comprises serialized bus protocol (e.g., a Universal...
US-9,747,236 HDMI extender with bidirectional power over twisted pair
Disclosed are various embodiments of transmit and receive connectivity devices that receive a media signal from a source device coupled to the HDMI port and to...
US-9,747,235 Information processing method and electronic device
An information processing method and an electronic device are provided, the information processing method includes: detecting a version parameter of a first USB...
US-9,747,234 Solid state drive controlling circuit and related solid state drive device and solid state drive access system
A solid state drive (SSD) controlling circuit and related SSD device and SSD access system are disclosed. The SSD controlling circuit includes: an AHCI (advance...
US-9,747,233 Facilitating routing by selectively aggregating contiguous data units
A method for facilitation of aggregation of contiguous data packets, such as contiguous I/O adapter stores, is disclosed. Commensurate with receiving data...
US-9,747,232 Data processing device
A data processing device includes: multiple data processing stages including a processing element, a stage memory and an event controller; and a bidirectional...
US-9,747,231 Bus access arbiter and method of bus arbitration
A bus access arbiter includes an access mode judgment unit and a round robin arbitration unit. The access mode judgment unit judges, when bus access is...
US-9,747,230 Memory rank and ODT configuration in a memory system
A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first...
US-9,747,229 Self-describing data format for DMA in a non-volatile solid-state storage
A method of applying a data format in a direct memory access transfer is provided. The method includes distributing user data throughout a plurality of storage...
US-9,747,228 Caching systems and methods for execution within an NVDRAM environment
Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system...
US-9,747,227 Method and system for transmitting information from a network device
Method and system for transmitting same data by at least two different ports of a network device coupled to a computing device or to at least two different...
US-9,747,226 Packet processing system, method and device to optimize packet buffer space
A buffer logic unit of a packet processing device that is configured to allocate single pages to two or more packets if the current packets stored on the page...
US-9,747,225 Interrupt controller
An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt...
US-9,747,224 Method and apparatus for managing register port
Provided is a method of managing a register port, the method including performing scheduling on register ports that are used during a plurality of cycles to...
US-9,747,223 Key encryption and decryption
Provided is a data storage drive for encrypting data, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session...
US-9,747,222 Dynamic ingestion throttling of data log
A technique for controlling acceptance of host application data into a data log in a data storage system includes selectively accepting or refusing newly...
US-9,747,221 Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform
A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing...
US-9,747,220 Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices
A secure demand paging system includes a secure internal memory having a table relating physical addresses to virtual addresses, a non-volatile memory, a...
US-9,747,219 Address remapping for efficient use of distributed memory
An apparatus such as a system-on-a-chip includes memory that is distributed through multiple functional hardware circuits. Each functional hardware circuit...
US-9,747,218 CPU security mechanisms employing thread-specific protection domains
A computer processor includes an instruction processing pipeline that interfaces to a hierarchical memory system employing an address space. The instruction...
US-9,747,217 Distributed history buffer flush and restore handling in a parallel slice design
An approach is provided in which a computing system captures content included in a history buffer entry that corresponds to a flush ITAG. The computing system,...
US-9,747,215 Stride reference prefetcher
A processor including a cache memory, processing logic, access logic, stride mask logic, count logic, arbitration logic, and a prefetcher. The processing logic...
US-9,747,214 Forecast modeling cache prefetch system and method
A system and method for prefetching data. Address logs are separated into streams and a model associated with each stream. Each stream address is forecasted...
US-9,747,213 Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and...
Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an...
US-9,747,212 Virtual unifed instruction and data caches including storing program instructions and memory address in CAM...
Execution of a store instruction to modify an instruction at a memory location identified by a memory address is requested. A cache controller stores the memory...
US-9,747,211 Cache memory, cache memory control unit, and method of controlling the cache memory
A cache memory includes: a tag storage section in which one of a plurality of indexes, each index containing a plurality of tag addresses and one...
US-9,747,210 Managing a lock to a resource shared among a plurality of processors
Provided are a computer program product, system, and method for managing a lock to a resource shared among a plurality of processors. Slots in a memory...
US-9,747,209 System and method for improved memory performance using cache level hashing
Various embodiments of methods and systems for cache-level memory management in a system on a chip ("SoC") are disclosed. Memory utilization is optimized in...
US-9,747,208 Instruction and logic for flush-on-fail operation
A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to...
US-9,747,207 Crash-proof cache data protection method and system
The inventions disclosed herein provide a crash-proof cache data protection method and system. The cache data backup steps include: when power interruption...
US-9,747,206 Methods for reprogramming data and apparatuses using the same
A method for reprogramming data, performed by a processing unit, is disclosed to include at least the following steps. After a page of data has failed to be...
US-9,747,205 Method for processing data and electronic device
A method for processing data and an electronic device are provided. The method includes: assigning first and second address sets in relation to data to be...
US-9,747,204 Multi-section garbage collection system including shared performance monitor register
A system includes memory and a hardware processor. The memory includes a load-monitored region register (LMRR) and a sampled data address register (SDAR). The...
US-9,747,203 Multi-section garbage collection system including multi-use source register
A computer system is configured to perform a garbage collection process within a computing environment. The computer system includes a memory having a...
US-9,747,202 Storage module and method for identifying hot and cold data
A storage module and method for identifying hot and cold data are provided. The storage module can be removable from a host or can be embedded in a host. In one...
US-9,747,201 Methods and systems for managing memory allocation
An electronic device with volatile memory repeatedly compares an amount of free volatile memory to a first predetermined threshold level of free volatile...
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