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Patent # Description
US-9,768,135 Semiconductor device having conductive bump with improved reliability
The present disclosure discloses a semiconductor device having conductive bumps formed on a conductive redistribution layer and associated method for...
US-9,768,134 Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects
A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in...
US-9,768,133 Semiconductor package and method of forming the same
An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer,...
US-9,768,132 Semiconductor structure and method of forming the same
A semiconductor structure includes a substrate, a bond pad over the substrate, and a passivation layer over the substrate and a peripheral region of the bond...
US-9,768,131 Method of producing a semiconductor device with protruding contacts
A wiring (3) comprising electrical conductors (4, 5, 6, 7) is formed in a dielectric layer (2) on or above a semiconductor substrate (1), an opening is formed...
US-9,768,130 Integrated power package
An integrated power package includes a substrate having a first surface and an integrated circuit located within the substrate. At least one electrical...
US-9,768,129 Semiconductor device including three-dimensional crack detection structure
A semiconductor device includes a semiconductor die, a semiconductor integrated circuit and a three-dimensional crack detection structure. The semiconductor die...
US-9,768,128 Chip and method for detecting an attack on a chip
According to one embodiment, a chip is described comprising a transistor level, a semiconductor region in, below, or in and below the transistor level, a test...
US-9,768,127 Wafer processing method
Disclosed herein is a wafer processing method including a first modified layer forming step of applying a laser beam having a transmission wavelength to a wafer...
US-9,768,126 Stacked semiconductor packages with cantilever pads
One or more embodiments are directed to semiconductor packages, including stacked packages, with one or more cantilever pads. In one embodiment a recess is...
US-9,768,125 Method of manufacturing semiconductor device with a metal layer along a step portion
A method of manufacturing a semiconductor device includes preparing a semiconductor layer having an element region and an outer peripheral region, forming a...
US-9,768,124 Semiconductor package in package
A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically...
US-9,768,123 Semiconductor device structures including a distributed bragg reflector
A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having...
US-9,768,122 Electronic part embedded substrate and method of producing an electronic part embedded substrate
An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part,...
US-9,768,121 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly...
US-9,768,120 Semiconductor device assembly including a chip carrier, semiconductor wafer and method of manufacturing a...
A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically...
US-9,768,119 Apparatus and method for mitigating dynamic IR voltage drop and electromigration affects
An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically...
US-9,768,118 Contact having self-aligned air gap spacers
A semiconductor device includes a semiconductor substrate, and a dielectric layer on an upper surface of the semiconductor substrate. A contact stack is formed...
US-9,768,117 Semiconductor device and method for manufacturing semiconductor device
According to one embodiment, a substrate includes a first portion and a second portion. The first portion has a columnar configuration. The second portion has...
US-9,768,116 Optimized wires for resistance or electromigration
Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes...
US-9,768,115 Semiconductor devices having nonlinear bitline structures
Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word...
US-9,768,114 Semiconductor device and method of manufacturing the same
A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in...
US-9,768,113 Self aligned via in integrated circuit
A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic...
US-9,768,112 Semiconductor device and method fabricating the same
According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first...
US-9,768,111 Mitigating electromigration effects using parallel pillars
Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one...
US-9,768,110 Physical unclonable interconnect function array
A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over...
US-9,768,109 Integrated circuits (ICS) on a glass substrate
An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of...
US-9,768,108 Conductive post protection for integrated circuit packages
An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as...
US-9,768,107 Method of providing a flexible semiconductor device and flexible semiconductor device thereof
Some embodiments include a method. The method can include providing a carrier substrate, providing a release layer over the carrier substrate, and providing a...
US-9,768,106 Chip-on-film package and display device including the same
A chip-on-film (COF) package includes a base film, a semiconductor chip mounted on a chip mounting region of a top surface of the base film, a plurality of top...
US-9,768,105 Rigid interconnect structures in package-on-package assemblies
System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid...
US-9,768,103 Fabrication method of embedded chip substrate
An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit...
US-9,768,102 Integrated circuit packaging system with support structure and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: forming a one-layer substrate with a symmetrical structure, the one-layer substrate...
US-9,768,101 High density integrated circuit package structure and integrated circuit
The present invention relates to the technical field of integrated circuit package, and more specifically, this invention relates to a high density integrated...
US-9,768,100 Semiconductor device
A semiconductor device includes a first conductive layer with first and second sections separated in a first direction. A first chip is on the first section and...
US-9,768,099 IC package with integrated inductor
In one implementation, a semiconductor package includes an integrated circuit (IC) attached to a die paddle segment of a first patterned conduct carrier and...
US-9,768,098 Packaged semiconductor device having stacked attached chips overhanging the assembly pad
A semiconductor device comprising a stack of semiconductor chips. The semiconductor chips have an electrically active side and an opposite electrically inactive...
US-9,768,096 Mobile terminal
A mobile terminal is provided. The mobile terminal includes a circuit board, where a chip is disposed on a first surface of the circuit board. A groove is...
US-9,768,095 Semiconductor device and manufacturing method thereof
A semiconductor device includes a semiconductor module. The semiconductor module includes a package made of resin. The package contains a semiconductor element...
US-9,768,094 Power electronics module with load connection elements
A power electronics module having a base plate, a circuit carrier arranged on the base plate and a plurality of conductor tracks which are electrically...
US-9,768,093 Resistive structure with enhanced thermal dissipation
An integrated circuit is provided. The integrated circuit includes a continuous resistor body having first and second distal terminals, and a group of...
US-9,768,092 Carrier package and carrier with plural heat conductors
A carrier is disclosed, including: a main body having a first surface and a second surface opposing the first surface; a conductive part formed on the first...
US-9,768,091 Method of forming an electronic package and structure
In one embodiment, an electronic package structure includes multiple rows of I/O pads and is formed without a flag portion. An electronic device may be attached...
US-9,768,090 Substrate design for semiconductor packages and method of forming same
An embodiment device package includes a package substrate and a first and a second die bonded to the package substrate. The package substrate includes a...
US-9,768,089 Wafer stack protection seal
A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second...
US-9,768,087 Compact high-voltage semiconductor package
There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor...
US-9,768,086 Methods and devices for fabricating and assembling printable semiconductor elements
The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate...
US-9,768,085 Top contact resistance measurement in vertical FETs
A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction...
US-9,768,084 Inline monitoring of transistor-to-transistor critical dimension
In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor...
US-9,768,083 Process for making and using a semiconductor wafer containing first and second DOEs of standard cell...
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill...
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