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Patent # Description
US-9,768,082 Method and machine for examining wafers
Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each...
US-9,768,081 Electron radiation monitoring electrode system to prevent gold spitting and resist cross-linking during evaporation
An electrode system configured to be positioned within a vacuum chamber of an electron-beam metal evaporation and deposition apparatus including a metal slug...
US-9,768,080 Semiconductor manufacturing apparatus and method thereof
A semiconductor manufacturing method includes several operations. One operation is catching an image of a predetermined location on a surface of a pad installed...
US-9,768,079 Extra gate device for nanosheet
A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is...
US-9,768,078 Inner L-spacer for replacement gate flow
An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner...
US-9,768,077 Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs)
A semiconductor device includes first and second gate structures on a substrate respectively corresponding to an n-type and a p-type transistor, a first...
US-9,768,076 Semiconductor device and method of forming the same
A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of...
US-9,768,075 Method and structure to enable dual channel fin critical dimension control
A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate having a {100} crystallographic surface...
US-9,768,074 Transistor structure and fabrication methods with an epitaxial layer over multiple halo implants
A method of forming a transistor can include forming a gate mask on a substrate having a vertical location aligned with that of a transistor control gate;...
US-9,768,073 Semiconductor device having dual channels, complementary semiconductor device and manufacturing method thereof
Provided is a semiconductor device having dual channels including a first portion and a second portion sharing a buried gate pillar. The buried gate pillar...
US-9,768,072 Fabrication of a vertical fin field effect transistor with reduced dimensional variations
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a...
US-9,768,071 Asymmetric high-K dielectric for reducing gate induced drain leakage
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes...
US-9,768,070 Method for manufacturing semiconductor device
Provided is a method for manufacturing a semiconductor device, which can secure a sufficient margin in a process of forming a self-aligned contact. The method...
US-9,768,069 Method of manufacturing semiconductor device
A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with an insulating layer formed thereon. The...
US-9,768,068 Display device
Disclosed is a display device that includes an array substrate that includes a display region and a first non-display region, and includes a signal line...
US-9,768,067 Chip package and manufacturing method thereof
A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a...
US-9,768,066 Semiconductor device and method of forming conductive vias by direct via reveal with organic passivation
A semiconductor device has a semiconductor wafer and a conductive via formed partially through the semiconductor wafer. A portion of the semiconductor wafer and...
US-9,768,065 Interconnect structures with variable dopant levels
Interconnect structures and related methods of manufacture improve device reliability and performance by selectively incorporating dopants into conductive...
US-9,768,064 Formation method of semiconductor device structure
Formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a low topography region and a high low...
US-9,768,063 Dual damascene fill
A method for filling vias formed in a dielectric layer with a metal or metal alloy that has a low solubility with copper over copper containing interconnects,...
US-9,768,062 Method for forming low parasitic capacitance source and drain contacts
A method for forming a low parasitic capacitance contact to a source-drain structure of a fin field effect transistor device. In some embodiments the method...
US-9,768,061 Low-k dielectric interconnect systems
A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric...
US-9,768,060 Systems and methods for electrochemical deposition on a workpiece including removing contamination from seed...
In one embodiment of the present disclosure, a method for electrochemical deposition on a workpiece includes (a) obtaining a workpiece including a feature; (b)...
US-9,768,059 High-chi block copolymers for interconnect structures by directed self-assembly
High-chi diblock copolymers are disclosed whose self-assembly properties are suitable for forming hole and bar openings for conductive interconnects in a...
US-9,768,058 Methods of forming air gaps in metallization layers on integrated circuit products
One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a layer of insulating material, performing at least...
US-9,768,057 Method for transferring a layer from a single-crystal substrate
A method for transferring a layer from a single-crystal substrate, called a donor substrate, onto a receiver substrate, includes supplying the single-crystal...
US-9,768,056 Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming...
US-9,768,055 Isolation regions for SOI devices
An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and...
US-9,768,054 High voltage device with low Rdson
High voltage devices and methods for forming thereof are disclosed. A high voltage device includes a substrate having a device region, where the device region...
US-9,768,053 Active structures of a semiconductor device and methods of manufacturing the same
A method of forming patterns of a semiconductor device, including partially etching an upper portion of a substrate to form first preliminary active patterns...
US-9,768,052 Minimal contact edge ring for rapid thermal processing
Embodiments of the present invention generally relate to a support ring for supporting a substrate during thermal processing in a process chamber. The support...
US-9,768,051 Wafer clamping apparatus
A wafer clamping apparatus, including a plurality of support pins under a wafer, the plurality of pins to support the wafer; and a side clamp at a lateral side...
US-9,768,050 Film for semiconductor back surface and its use
It is an object of the present invention to provide a film for semiconductor back surface having reworkability, and an application of the film. A film for...
US-9,768,049 Support plate and method for forming support plate
A method for processing a wafer having a device region and a peripheral surplus region surrounding the device region on a front surface thereof. The method...
US-9,768,048 Package on-package structure
A device comprises a top package mounted on a bottom package, wherein the bottom package comprises a plurality of interconnection components and the bottom...
US-9,768,047 SiC epitaxial wafer and method for producing same, and device for producing SiC epitaxial wafer
A SiC epitaxial wafer manufacturing method of the present invention includes: manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a surface...
US-9,768,046 Wafer storage container
A wafer storage container includes a shell body including a first side body and a second side body that face, an upper body connected with upper parts of the...
US-9,768,045 Substrate storing container
The lid body side wafer support parts allow flexibility to be exhibited and supports the wafers. If a closed state substrate is defined as being a wafer which...
US-9,768,044 Apparatus and methods for annealing wafers
A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the...
US-9,768,043 Quartz upper and lower domes
Embodiments of the present disclosure relate to a dome assembly. The dome assembly includes an upper dome including a central window, and an upper peripheral...
US-9,768,042 Substrate processing method and substrate processing apparatus
A substrate processing method is implemented in a substrate processing apparatus including a substrate holding and rotating unit having a spin base rotatable...
US-9,768,040 Substrate treatment method
A substrate treatment method and apparatus including a change controlling unit which changes at least one of a protection liquid application position relative...
US-9,768,039 Substrate processing apparatus
A substrate processing apparatus includes a rotary cup that is provided at a substrate holding unit to surround a substrate held thereon and to be rotated along...
US-9,768,038 Semiconductor device and method of making embedded wafer level chip scale packages
A semiconductor device includes a carrier and a plurality of semiconductor die disposed over the carrier. An encapsulant is deposited over the semiconductor...
US-9,768,037 Electronic device package including metal blocks
A method of manufacturing an electronic device package includes structuring a metal layer to generate a structured metal layer having a plurality of openings....
US-9,768,036 Power semiconductor substrates with metal contact layer and method of manufacture thereof
A power semiconductor substrate comprising an insulating planar base, at least one conductor track and at least one contact area as part of the conductor track,...
US-9,768,035 Electronic module and method for producing an electronic module
One aspect of the invention relates to an electronic module comprising a module housing and an electrically conductive connection element. The connection...
US-9,768,034 Removal methods for high aspect ratio structures
Exemplary cleaning or etching methods may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber....
US-9,768,033 Methods for high precision etching of substrates
This disclosure relates to a plasma processing system and methods for high precision etching of microelectronic substrates. The system may include a combination...
US-9,768,032 Method of forming pattern and method of manufacturing integrated circuit device by using the same
A method of forming a pattern including forming a feature layer on a substrate having first and second regions; forming a first guide pattern on the first...
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