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| Patent # | Description |
|---|---|
| US-9,780,080 |
Method for making an optical proximity sensor by attaching an optical
element to a package top plate and... A method for making an optical proximity sensor includes forming a package top plate having an optical transmit opening and an optical receive opening extending... |
| US-9,780,079 |
Semiconductor die assembly and methods of forming thermal paths Semiconductor die assemblies and methods of forming the same are described herein. As an example, a semiconductor die assembly may include a thermally... |
| US-9,780,078 |
Method for producing optoelectronic semiconductor devices and
optoelectronic semiconductor device The invention relates to a method for producing a plurality of optoelectronic semiconductor components (1), comprising the following steps: a) providing a... |
| US-9,780,077 |
System-in-packages containing preassembled surface mount device modules
and methods for the production thereof Methods for producing System-in-Packages (SiPs) containing embedded Surface Mount Device (SMD) modules are provided, as SiPs containing SMD modules. In one... |
| US-9,780,076 |
Package-on-package structure with through molding via Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the... |
| US-9,780,075 |
Interconnect structures for assembly of multi-layer semiconductor devices A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second... |
| US-9,780,074 |
Semiconductor package using a coreless signal distribution structure A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at... |
| US-9,780,073 |
Using interrupted through-silicon-vias in integrated circuits adapted for
stacking In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to... |
| US-9,780,072 |
3D semiconductor package interposer with die cavity Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or... |
| US-9,780,071 |
Stacked semiconductor package including reconfigurable package units A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The... |
| US-9,780,070 |
Method for manufacturing semiconductor device A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so... |
| US-9,780,069 |
Semiconductor device A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and... |
| US-9,780,068 |
Adhesive for electronic component An adhesive composition for a pre-applied underfill sealant comprising: (a) a radical polymerizable monomer having one or more functional groups selected from... |
| US-9,780,067 |
Semiconductor chip metal alloy thermal interface material Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The... |
| US-9,780,066 |
Thermocompression bonding systems and methods of operating the same A thermocompression bonding system for bonding semiconductor elements is provided. The thermocompression bonding system includes (1) a bond head assembly... |
| US-9,780,065 |
Systems and methods for bonding semiconductor elements A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first... |
| US-9,780,064 |
Method of forming package assembly A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to... |
| US-9,780,063 |
Semiconductor device and method of forming bump structure with insulating
buffer layer to reduce stress on... A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor... |
| US-9,780,062 |
Method of manufacturing a functional inlay The method of manufacturing a functional inlay comprises the steps of: a support layer with at least a first and a second side a wire antenna in said support... |
| US-9,780,061 |
Molded chip package and method of manufacturing the same A method of manufacturing a molded chip package is provided which comprises arranging an electronic chip on a supporting structure; forming an isolation layer... |
| US-9,780,060 |
Packaged IC with solderable sidewalls A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls... |
| US-9,780,059 |
Bonding structure and method A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the... |
| US-9,780,058 |
Assembly with a carrier substrate and at least one electrical component
arranged thereon, and electrical component An electronic assembly has a carrier substrate with contact surfaces and at least one electrical component on the carrier substrate. On its surface that is... |
| US-9,780,057 |
Semiconductor device and method of forming pad layout for flipchip
semiconductor die A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the... |
| US-9,780,056 |
Solder ball, manufacturing method thereof, and semiconductor device A solder ball includes a silver ball structure and a shell structure. The shell structure wraps a surface of the silver ball structure, and a material of the... |
| US-9,780,055 |
Lead-free solder ball A lead-free solder ball is provided which suppresses interfacial peeling in a bonding interface of a solder ball, fusion defects which develop between the... |
| US-9,780,054 |
Semiconductor package with embedded die and its methods of fabrication Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that... |
| US-9,780,053 |
Method of forming a bondpad and bondpad Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact... |
| US-9,780,052 |
Collars for under-bump metal structures and associated systems and methods The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and... |
| US-9,780,051 |
Methods for forming semiconductor devices with stepped bond pads A method for forming a semiconductor structure includes forming a bond pad over a last metal layer of the semiconductor structure wherein the bond pad includes... |
| US-9,780,050 |
Method of fabricating chip package with laser A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first... |
| US-9,780,049 |
Semiconductor package A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the... |
| US-9,780,048 |
Side-assembled passive devices An integrated circuit device includes a first substrate having a ground plane. The integrated circuit device also includes a second substrate. The second... |
| US-9,780,047 |
Semiconductor package A semiconductor package includes: a first substrate including a first ground conductor disposed on at least a second surface of a first surface and the second... |
| US-9,780,046 |
Seal rings structures in semiconductor device interconnect layers and
methods of forming the same An embodiment device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a... |
| US-9,780,045 |
Method for fabrication of an integrated circuit rendering a reverse
engineering of the integrated circuit more... An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at... |
| US-9,780,044 |
Transient electronic device with ion-exchanged glass treated interposer A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger... |
| US-9,780,043 |
Wiring board, semiconductor package, and semiconductor device A wiring board includes: a first insulating layer which is made of an insulating resin containing a thermosetting resin as a main component; a recess portion... |
| US-9,780,042 |
Tunable composite interposer A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a... |
| US-9,780,041 |
Method for making EMI shielding layer on a package A method for making EMI shielding layer on a package is disclosed to include the steps of: a) disposing a UV curable adhesive which can be thermally released on... |
| US-9,780,040 |
Integrated circuit package substrates having a common die dependent region
and methods for designing the same Techniques for designing integrated circuit (IC) package substrates are provided. One of the provided techniques include routing a first set of interconnects in... |
| US-9,780,039 |
Semiconductor device and fabrication method for the same The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in... |
| US-9,780,038 |
AVD hardmask for damascene patterning A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a... |
| US-9,780,037 |
Method of processing target object A plasma processing method can suppress both surface roughness of a wiring and surface roughness of a metal mask. The method includes generating plasma of a... |
| US-9,780,036 |
Semiconductor device A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first... |
| US-9,780,035 |
Structure and method for improved stabilization of cobalt cap and/or
cobalt liner in interconnects A method for fabricating a metallization layer of a semiconductor device, in which copper is used for an interconnect material and cobalt is used to encapsulate... |
| US-9,780,034 |
Three-dimensional memory device containing annular etch-stop spacer and
method of making thereof A method of forming a monolithic three-dimensional memory device includes forming a first alternating stack over a substrate, forming an insulating cap layer,... |
| US-9,780,033 |
Semiconductor device and method of manufacturing the same A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the... |
| US-9,780,032 |
Wiring substrate A wiring substrate includes a first insulation layer, a wiring layer formed on an upper surface of the first insulation layer, a barrier film that covers the... |
| US-9,780,031 |
Wiring structures Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in... |
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