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Patent # Description
US-9,780,030 Integrated circuit
An integrated circuit according to an embodiment includes: an anti-fuse element including a first terminal and a second terminal; a fuse element including a...
US-9,780,029 Semiconductor constructions having conductive lines which merge with one another
Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the...
US-9,780,028 Interconnects through dielectric vias
A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer away from a raised feature. An interconnect is in contact...
US-9,780,027 Hybrid airgap structure with oxide liner
A technique relates to an airgap structure. A dielectric layer is formed on an underlying layer. Copper filled trenches are formed in the dielectric layer, and...
US-9,780,026 Interconnection structure and method of forming the same
An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure and a conductive structure. The liner layer is present on...
US-9,780,025 Interconnection structure and manufacturing method thereof
An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The...
US-9,780,024 Semiconductor package and manufacturing method thereof
A semiconductor package and a method of making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various...
US-9,780,023 Chip on film unit
In the technical field of liquid crystal technology, a chip on film unit is provided. The chip on film unit comprises a soft dielectric layer, a plurality of...
US-9,780,022 Substrate structure
A substrate structure and a manufacturing method thereof are provided. The substrate structure comprises a dielectric material layer, a first conductive wiring...
US-9,780,021 Method of manufacturing element chip, method of manufacturing electronic component-mounted structure, and...
To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing...
US-9,780,020 Wiring substrate and semiconductor device
A wiring substrate includes a wiring layer located on an insulation layer, and a protective insulation layer covering the wiring layer and the insulation layer....
US-9,780,019 Semiconductor component and method of manufacture
A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a...
US-9,780,018 Power semiconductor package having reduced form factor and increased current carrying capability
A power semiconductor package is disclosed. The power semiconductor package includes a leadframe having partially etched segments and at least one non-etched...
US-9,780,017 Packaged device with additive substrate surface modification
A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a...
US-9,780,016 Lead frame, electronic control device using lead frame, and lead-frame mounting method
Conventional lead frames could neither be self-supporting nor be picked up by an automatic mounter through suction and mounted on a circuit board. Lead frame 15...
US-9,780,015 Integrated circuit chip assembled on an interposer
A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal...
US-9,780,014 Simultaneous controlled depth hot embossing and active side protection during packaging and assembly of wide...
A method of mounting a plurality of semiconductor or microelectronic chips or dies, the method including providing a carrier, temporarily adhering the plurality...
US-9,780,012 Semiconductor device and method for manufacturing the same
A semiconductor device includes: an interlayer insulating film covering: a cathode region and an anode region to form a pn junction with each other; a cathode...
US-9,780,011 Brazing material, brazing material paste, ceramic circuit substrate, ceramic master circuit substrate, and...
To provide a brazing material for maintaining bonding strength between ceramic substrate and metal plate at a conventionally attainable level, while addition...
US-9,780,010 Hermetic package with improved RF stability and performance
The present disclosure relates to a hermetic package with improved RF stability and performance. The package includes a carrier, a bottom dielectric ring over...
US-9,780,009 Integrated circuit packages and methods for forming the same
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector...
US-9,780,008 Semiconductor device, method for manufacturing the same, and rinsing liquid
A method for manufacturing a semiconductor device including: a process of applying a sealing composition for a semiconductor to a semiconductor substrate, to...
US-9,780,007 LCR test circuit structure for detecting metal gate defect conditions
A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each...
US-9,780,006 Method for evaluating SOI substrate
An SOI substrate evaluating method includes: forming a device onto a measuring SOI substrate, and previously determining a relationship between an interface...
US-9,780,005 Method for evaluating quality of oxide semiconductor thin film and laminated body having protective film on...
Provided is a method for reliably and simply evaluating the quality of an oxide semiconductor thin film and a laminated body having a protective film on the...
US-9,780,004 Methods and apparatus for optimization of inspection speed by generation of stage speed profile and selection...
Disclosed are apparatus and methods for the generation of a stage speed profile and/or the selection of care areas for automated wafer inspection. The stage...
US-9,780,003 Bipolar junction transistor formed on fin structures
A method of forming a Bipolar Junction Transistor (BJT) includes forming an elongated collector line, forming an elongated emitter line parallel to the...
US-9,780,002 Threshold voltage and well implantation method for semiconductor devices
Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN;...
US-9,780,001 Devices having inhomogeneous silicide schottky barrier contacts
A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided. A plurality of...
US-9,780,000 Method for forming spacers for a transitor gate
A method for forming spacers of a gate of a field-effect transistor is provided, including at least one step of forming a protective layer covering the gate;...
US-9,779,999 Complementary nanowire semiconductor device and fabrication method thereof
Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a...
US-9,779,998 Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with...
US-9,779,997 Semiconductor device and a method for fabricating the same
In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate...
US-9,779,996 Integrated circuit devices and methods of manufacturing the same
An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode...
US-9,779,995 Highly scaled tunnel FET with tight pitch and method to fabricate same
A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying...
US-9,779,994 Wafer processing method
A wafer processing method including the steps of storing information on the intervals and positions of metal patterns formed on part of division lines on a...
US-9,779,993 Wafer processing method including attaching a protective tape to a front side of a functional layer to prevent...
A method for dividing a wafer including: attaching a protective tape to a functional layer of the wafer with the adhesive layer of the tape in contact with the...
US-9,779,992 Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming a first via having a first diameter in a first main surface of a semiconductor substrate...
US-9,779,990 Integrated antenna on interposer substrate
Some embodiments relate to a semiconductor module comprising a low-cost integrated antenna that uses a conductive backside structure in conjunction with a...
US-9,779,989 Method for manufacturing metal interconnects
A method for manufacturing metal interconnects. The method includes following steps. A substrate including a dielectric layer formed thereon is provided, and a...
US-9,779,988 Semiconductor devices with inner via
A semiconductor device includes a semiconductor substrate having an inactive area and a pair of active areas separated by the inactive area, a control terminal...
US-9,779,987 Titanium silicide formation in a narrow source-drain contact
Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a...
US-9,779,986 Plasma treatment method and method of manufacturing electronic component
Provided is a plasma treatment method including: placing a substrate carrier holding a substrate on a stage; adjusting a distance between a cover and the stage...
US-9,779,985 Method for making patterns by self-assembly of block copolymers
A method for making patterns includes forming on a substrate surface a first mask delimiting at least two areas to be metallised; forming an assembly guide...
US-9,779,984 Method of forming trenches with different depths
A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first trench...
US-9,779,983 Methods for forming air gaps in shallow trench isolation trenches for NAND memory
A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the...
US-9,779,982 Fabrication method of a stack of electronic devices
This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a...
US-9,779,981 Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over...
US-9,779,980 Uniform shallow trench isolation regions and the method of forming the same
A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the...
US-9,779,979 Apparatus for liquid treatment of wafer shaped articles
An apparatus for processing wafer-shaped articles comprises a spin chuck adapted to hold and spin a wafer-shaped article of a predetermined diameter during a...
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