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Patent # Description
US-9,786,682 Manufacturing method of semiconductor device including barrier pattern
The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first...
US-9,786,681 Multilevel memory stack structure employing stacks of a support pedestal structure and a support pillar structure
Memory-opening semiconductor material portions and support opening fill structures can be simultaneously formed through a first alternating stack of first...
US-9,786,680 Semiconductor device
A semiconductor device includes: a semiconductor substrate, a first portion and a second portion of an upper layer portion of the semiconductor substrate being...
US-9,786,679 Method for manufacturing semiconductor memory device
According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes...
US-9,786,678 Nonvolatile semiconductor memory device and method of manufacturing the same
According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer...
US-9,786,676 Vertical memory devices and methods of manufacturing the same
A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction...
US-9,786,675 Non-volatile memory devices including charge storage layers
A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the...
US-9,786,674 Discrete storage element formation for thin-film storage device
Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion...
US-9,786,673 Semiconductor memory device including pillars
A semiconductor memory device may include: a first group of pillars having diameters which are gradually increased toward the a first side; and interlayer...
US-9,786,672 Method of manufacturing semiconductor devices having contact plugs overlapping associated bitline structures...
A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the...
US-9,786,671 Niobium-containing film forming compositions and vapor deposition of niobium-containing films
Niobium-containing film forming compositions are disclosed, along with methods of synthesizing the same, and methods of forming Niobium-containing films on one...
US-9,786,670 Semiconductor memory device
To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide...
US-9,786,669 Memory device and manufacturing method the same
A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like;...
US-9,786,668 Semiconductor device including multilayer wiring layer
The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a...
US-9,786,667 Floating body memory cell having gates favoring different conductivity type regions
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is...
US-9,786,666 Method to form dual channel semiconductor material fins
A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a...
US-9,786,665 Dual deep trenches for high voltage isolation
A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a...
US-9,786,664 Fabricating a dual gate stack of a CMOS structure
A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel...
US-9,786,663 Layout construction for addressing electromigration
A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level...
US-9,786,662 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate pattern is formed on the substrate, a first spacer is...
US-9,786,661 Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction
A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an...
US-9,786,660 Transistor with bypassed gate structure field
A transistor device includes a source contact extending in a first direction, a gate finger extending in the first direction adjacent the source contact, and a...
US-9,786,659 Semiconductor component with dielectric layer stack and voltage divider
A semiconductor component has a semiconductor body zone, a first electrically conductive layer adjacent to the semiconductor body zone, a first dielectric layer...
US-9,786,658 Fabrication method of a stack of electronic devices
This method comprises the following steps: a) providing a first structure successively comprising a first substrate, a first electronic device, and a first...
US-9,786,657 Semiconductor structure including a transistor including a gate electrode region provided in a substrate and...
A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor...
US-9,786,656 Integration of bipolar transistor into complimentary metal-oxide-semiconductor process
A fin heterojunction bipolar transistor (fin HBT) and a method of fabricating the fin HBT for integration with a fin complimentary metal-oxide-semiconductor...
US-9,786,655 Display panel and display device
A display panel and a display device are provided. The display panel includes an array substrate and an opposite substrate arranged oppositely; a sealant...
US-9,786,654 Electrostatic discharge protection semiconductor device
An ESD protection semiconductor device includes a substrate, a first isolation structure disposed in the substrate, a gate disposed on the substrate and...
US-9,786,653 Self-balanced diode device
A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity...
US-9,786,652 ESD protection with asymmetrical bipolar-based device
An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well...
US-9,786,651 Electrostatic discharge device
An electrostatic discharge device includes a power clamping circuit and an isolation circuit. The power clamping circuit includes a first Zener diode and a...
US-9,786,650 Process for making and using a semiconductor wafer containing first and second DOEs of standard cell...
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill...
US-9,786,649 Process for making and using a semiconductor wafer containing first and second DOEs of standard cell...
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill...
US-9,786,648 Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including...
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells...
US-9,786,647 Semiconductor layout structure
A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns...
US-9,786,646 Matrix addressed device repair
A repairable matrix-addressed system includes a system substrate, an array of electrically conductive row lines, and an array of electrically conductive column...
US-9,786,645 Integrated circuit
An integrated circuit is provided. A standard cell includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS transistors are...
US-9,786,644 Methods of fabricating a semiconductor package
Provided is a method of fabricating a semiconductor package. The method include providing a lower package with an inner solder ball, providing a conductive...
US-9,786,643 Semiconductor devices comprising protected side surfaces and related methods
Methods of protecting semiconductor devices may involve forming trenches in streets between stacks of semiconductor dice on regions of a semiconductor wafer. A...
US-9,786,642 Light emitting diode package substrate and light emitting diode package element
A miniaturized LED package substrate allowing for the better installation of an electrostatic protection device includes an upper substrate, a lower substrate,...
US-9,786,641 Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics...
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For...
US-9,786,640 Transistor arrangement
A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure...
US-9,786,639 Solid state light fixtures suitable for high temperature operation having separate blue-shifted-yellow/green...
Solid state light fixtures include a plurality of blue-shifted-yellow/green light emitting diode ("LED") packages and a plurality of blue-shifted-red LED...
US-9,786,638 Light-emitting device and display device
Disclosed herein is a light-emitting device including a plurality of first light-emitting elements mounted in a matrix form on a common wiring board. Each of...
US-9,786,637 Light emitting device
There is presented a light emitting device, having plural light emitting elements disposed on a substrate, in which a protection element, such as a zener diode,...
US-9,786,636 Semiconductor device and structure
An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal...
US-9,786,635 Integrated circuit package assembly
An integrated circuit package assembly includes a substrate and a first integrated circuit package over the substrate. The integrated circuit package assembly...
US-9,786,634 Interconnection structures and methods for making the same
The present disclosure provides a method for interconnecting components. First and second substrates are provided. First and second components are respectively...
US-9,786,633 Interconnect structures for fine pitch assembly of semiconductor structures and related techniques
A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first...
US-9,786,632 Semiconductor package structure and method for forming the same
A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor...
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