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Patent # Description
US-9,786,631 Device package with reduced thickness and method for forming same
A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The...
US-9,786,630 Semiconductor device manufacturing method and semiconductor wafer
A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering...
US-9,786,629 Dual-side reinforcement flux for encapsulation
Dual-side reinforcement (DSR) materials and methods for semiconductor fabrication. The DSR materials exhibit the properties of conventional underfill materials...
US-9,786,628 Air trench in packages incorporating hybrid bonding
A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second...
US-9,786,627 Method for creating a connection between metallic moulded bodies and a power semiconductor which is used to...
The invention relates to a method for connecting a power semi-conductor chip having upper-sided potential surfaces to thick wires or strips, consisting of the...
US-9,786,626 Semiconductor device with a wire bonding and a sintered region, and manufacturing process thereof
An electronic device includes: a semiconductor body; a front metallization region; a top buffer region, arranged between the front metallization region and the...
US-9,786,625 Semiconductor packages and methods of packaging semiconductor devices
Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second...
US-9,786,624 Semiconductor package
A semiconductor package includes a substrate having a groove in an upper surface. A semiconductor device is mounted on the substrate to cover one portion of the...
US-9,786,623 Semiconductor device and method of forming PoP semiconductor device with RDL over top package
A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a...
US-9,786,622 Semiconductor package
A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder...
US-9,786,621 Elongated bump structures in package structure
A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along...
US-9,786,620 Semiconductor device and a method for manufacturing a semiconductor device
According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one...
US-9,786,619 Semiconductor structure and manufacturing method thereof
The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over...
US-9,786,618 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a die including a die pad disposed over the die; a conductive member disposed over and electrically connected with the die...
US-9,786,617 Chip packages and methods of manufacture thereof
A chip package may include a die and a redistribution structure over the die. The redistribution structure may include a die, a redistribution structure over...
US-9,786,616 Semiconductor apparatus, method for manufacturing the same, electronic device, and moving body
A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer...
US-9,786,614 Integrated fan-out structure and method of forming
Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is...
US-9,786,613 EMI shield for high frequency layer transferred devices
Various methods and devices that involve EMI shields for radio frequency layer transferred devices are disclosed. One method comprises forming a radio frequency...
US-9,786,612 Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in...
US-9,786,611 Method for manufacturing a semiconductor package
A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device...
US-9,786,610 Semiconductor package and fabrication method thereof
A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom...
US-9,786,609 Stress shield for integrated circuit package
A stress shield for a plastic integrated circuit package is disclosed. A shield plate is attached by an adhesive to a top surface of an integrated circuit die...
US-9,786,608 Wafer structure for electronic integrated circuit manufacturing
A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device...
US-9,786,607 Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer
An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer...
US-9,786,606 Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI...
US-9,786,605 Advanced through substrate via metallization in three dimensional semiconductor integration
In one aspect of the invention, a method to create an advanced through silicon via structure is described. A high aspect ratio through substrate via in a...
US-9,786,604 Metal cap apparatus and method
A method of forming a metal layer may include forming an opening in a substrate; forming a liner over sidewalls of the opening; filling the opening with a first...
US-9,786,603 Surface nitridation in metal interconnects
Conductive contacts and methods of forming vias include forming a trench that penetrates a dielectric layer to expose a surface of an underlying conductor....
US-9,786,601 Semiconductor device having wires
A semiconductor device includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern...
US-9,786,600 Semiconductor devices including bit line contact plug and peripheral transistor
A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active...
US-9,786,599 Package structures and method of forming the same
An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least...
US-9,786,598 Semiconductor device with air gaps and method for fabricating the same
A semiconductor device includes: a first plug; a bit line which is in contact with the first plug and over the first plug and extended in one direction; a...
US-9,786,597 Self-aligned pitch split for unidirectional metal wiring
Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a...
US-9,786,596 Fuse formed from III-V aspect ratio structure
A fuse structure is provided above a first portion of a semiconductor material. The fuse structure includes a first end region containing a first portion of a...
US-9,786,595 Antifuse having comb-like top electrode
Antifuse structures are provided for use in applications such as field programmable gate arrays and programmable read-only memories. High aspect ratio channels...
US-9,786,594 Semiconductor device
A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first...
US-9,786,593 Semiconductor device and method for forming the same
A semiconductor device with a ring structure surrounding a through silicon via (TSV) electrode and a method for forming the same are disclosed. The method...
US-9,786,592 Integrated circuit structure and method of forming the same
An integrated circuit structure with a back side through silicon via (B/S TSV) therein and a method of forming the same is disclosed. The method includes the...
US-9,786,591 Capacitor in post-passivation structures and methods of forming the same
A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying...
US-9,786,590 Semiconductor package including a conductive fabric
A semiconductor package may be provided. The semiconductor package may include a substrate formed with one or more connection pads. The semiconductor package...
US-9,786,589 Method for manufacturing package structure
A method for manufacturing a package structure carries out in following way. A flexible circuit board is provided. The flexible circuit board defines a bent...
US-9,786,588 Circuit substrate and package structure
The invention provides a circuit substrate and a package structure. The circuit substrate includes a molding compound having a chip-side surface and a solder...
US-9,786,587 Semiconductor device and method for manufacturing the semiconductor device
A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically...
US-9,786,586 Semiconductor package and fabrication method thereof
A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A...
US-9,786,585 Lead-frame
One example discloses a lead-frame, comprising: a die-pad having a die coupling surface; a set of terminals each having an outer terminal edge and an inner...
US-9,786,584 Lateral element isolation device
Representative implementations of devices and techniques provide isolation between a carrier and a component mounted to the carrier. A multi-layer device having...
US-9,786,583 Power semiconductor package device having locking mechanism, and preparation method thereof
A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin,...
US-9,786,582 Planar leadframe substrate having a downset below within a die area
A leadframe for encasing in a mold material includes a plurality of interconnected support members. A die pad is connected to the support members and includes a...
US-9,786,581 Through-silicon via (TSV)-based devices and associated techniques and configurations
Embodiments of the present disclosure are directed toward through-silicon via (TSV)-based devices and associated techniques and configurations. In one...
US-9,786,580 Self-alignment for redistribution layer
An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the...
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