Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,786,376 Non-volatile semiconductor memory device and erasing method thereof
A non-volatile semiconductor memory device achieving low power consumption and erasing method thereof is provided. The flash memory of the present invention...
US-9,786,375 Multiple blocks per string in 3D NAND memory
Embodiments describe techniques and configurations for an apparatus including a three-dimensional (3D) memory array having a plurality of strings of memory...
US-9,786,374 Nonvolatile memory device, operating method thereof, and test system for optimizing erase loop operations
A nonvolatile memory device includes a plurality of memory blocks. The nonvolatile memory device includes a controller configured to perform an erase operation...
US-9,786,373 EEPROM backup method and device
An electrically erasable programmable read-only memory (EEPROM) device includes a plurality of data areas in the EEPROM associated with a corresponding...
US-9,786,372 Nonvolatile memory device and wordline driving method thereof
According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a...
US-9,786,371 Power-on reset circuit with variable detection reference and semiconductor memory device including the same
Provided herein are a power-on reset circuit and a semiconductor memory device including the same. The power-on reset circuit may include: a voltage dividing...
US-9,786,370 CES-based latching circuits
According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated...
US-9,786,369 Enhanced MLC programming
Mechanisms or techniques for improving operations such as program or erase operations that are intended to set a state of one or more multi-level memory cells...
US-9,786,368 Two stage forming of resistive random access memory cells
Provided are memory cells, such as resistive random access memory (ReRAM) cells, each cell having multiple metal oxide layers formed from different oxides, and...
US-9,786,367 Method of reading an electronic memory device including a plurality of memory cells of resistive random access...
A method for reading an electronic memory device including N memory cells Ci with 1.gtoreq.i.gtoreq.N and N.gtoreq.2, each cell Ci having a resistance Ri, the...
US-9,786,366 Apparatuses, memories, and methods for address decoding and selecting an access line
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address...
US-9,786,365 Integrated circuit
An integrated circuit according to an embodiment includes: a first wiring line group including at least three first wiring lines; a second wiring line group...
US-9,786,364 Low voltage selftime tracking circuitry for write assist based memory operation
Disclosed herein is an electronic device including a bit line and a complementary bit line, first and second cross coupled inverters, a first pass gate coupled...
US-9,786,363 Word-line enable pulse generator, SRAM and method for adjusting word-line enable time of SRAM
A word-line enable pulse generator for a SRAM is provided. A delay unit receives an enable signal to provide an intermediate signal. A first inverter receives...
US-9,786,362 Memory circuit and data processing system
A memory circuit comprises an array of data storage elements; access circuitry to access a data bit, stored by a data storage element enabled for access, by an...
US-9,786,361 Programmable decoupling capacitance of configurable logic circuitry and method of operating same
An integrated circuit comprising at least one logic tile including a plurality of multiplexers interconnected into a network configuration, wherein each...
US-9,786,360 Static semiconductor memory device using a single global data line
A memory bank of a semiconductor memory device includes: a plurality of memory cells; first and second local bit lines; a differential amplifier configured to...
US-9,786,359 Static random access memory (SRAM) tracking cells and methods of forming same
An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current tracking...
US-9,786,358 6T bitcell for single port static random access memories (SRAM) with single-ended read and single-ended write
A 6T bitcell for single port SRAM that performs single ended read and single ended write is described. The presently described bitcell gives huge advantage in...
US-9,786,357 Bit-cell voltage distribution system
In some embodiments, a method includes receiving, at a voltage distribution circuit, a power enable signal. In response to the power enable signal, the voltage...
US-9,786,356 Memory device with adaptive voltage scaling based on error information
A method of operation of a memory device includes, for each operating frequency of multiple operating frequencies, determining a target voltage level of a...
US-9,786,355 Signaling method using constant reference voltage and devices thereof
A semiconductor device includes a receiver configured to receive a reference voltage via a first input terminal, receive an input signal via a second input...
US-9,786,354 Memory module
A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed...
US-9,786,353 Reconfigurable clocking architecture
Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit...
US-9,786,352 Semiconductor memory device including refresh operations having first and second cycles
Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells,...
US-9,786,351 Semiconductor memory device for performing refresh operation and operating method therof
A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart...
US-9,786,350 Memory device
A memory device with a novel structure that is suitable for a register file is provided. The memory device includes a first memory circuit and a second memory...
US-9,786,349 Cell performance recovery using cycling techniques
Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of...
US-9,786,348 Dynamic adjustment of memory cell digit line capacitance
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state....
US-9,786,347 Cell-specific reference generation and sensing
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for...
US-9,786,346 Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense...
US-9,786,345 Compensation for threshold voltage variation of memory cell components
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of...
US-9,786,344 Programming of magnetic random access memory (MRAM) by boosting gate voltage
A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a...
US-9,786,343 STT MRAM common source line array bias scheme
Improved STT MRAM CSL array bias schemes are provided. In one aspect, a method for operating a CSL STT MRAM array includes: providing the STT MRAM array having...
US-9,786,342 Memory control circuit and cache memory
A memory control circuit to control a first memory comprising a plurality of MRAM cells, each MRAM cell including of a magnetoresistive element to store data,...
US-9,786,340 Driving circuit for non-volatile memory
A driving circuit includes a driving stage with a first level shifter and a second level shifter. The first level shifter includes an input terminal receiving a...
US-9,786,339 Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation
A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a...
US-9,786,338 Multiple register memory access instructions, processors, methods, and systems
A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction...
US-9,786,337 Sensing buffer, peripheral circuit, and/or memory device
A sensing buffer, or peripheral circuit or memory device may be provided. The sensing buffer may be configured to maintain a predetermined current according to...
US-9,786,336 Memory device capable of operation in wide temperature range and data processing system and method of operating...
A data processing system includes a first memory, a second memory, a temperature sensor, and a controller. The temperature sensor is configured to sense a...
US-9,786,335 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,786,334 Interconnections for 3D memory
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs...
US-9,786,333 Dual-bit 3-T high density MTPROM array
A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor...
US-9,786,332 Semiconductor device package with mirror mode
Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor...
US-9,786,331 Shielded three-layer patterned ground structure
The present disclosure generally relates to a shielded three-layer patterned ground structure in a PCB. The PCB may be disposed in a hard disk drive. To reduce...
US-9,786,330 Shield for external welds of hermetically sealed electronics devices
Described herein is a system that includes a hard disk drive. The hard disk drive includes a base and a cover welded to the base by a weld bead. The base and...
US-9,786,329 Digital postcard
Disclosed is an electronic digital postcard device comprising, a body housing a display, the housing defining a dimension of the device, where the dimension is...
US-9,786,328 Methods and systems for previewing a recording
Certain aspects of the present disclosure relate to methods and systems for previewing a recording. In one aspect, the methods and systems are configured to...
US-9,786,327 Utilizing audio digital impact to create digital media presentations
Systems and methods disclosed create one or more digital media presentations based on impact values. In particular, in one or more embodiments, systems and...
US-9,786,326 Method and device of playing multimedia and medium
The present disclosure relates to a method and a device for playing multimedia. The method may comprise: obtaining at least one of audio data and subtitle data...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.