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Patent # Description
US-9,785,617 Efficient creation of documents
Some embodiments provide a method that efficiently designs a document. The method provides the user with a selection of templates, each with a default...
US-9,785,616 Method and apparatus for determining threshold baselines based upon received measurements
A method and apparatus can be configured to receive a data set of values relating to a process. The data set of values correspond to values measured while the...
US-9,785,615 Memristive computation of a vector cross product
Memristive computation of a cross product is disclosed. One example is a crossbar array of memory elements that include a number of column lines perpendicular...
US-9,785,614 Fast Fourier transform device, fast Fourier transform method, and recording medium storing fast Fourier...
[Problem] A fast Fourier transform method is provided that are able to input data to be processed or output processing results in no particular order....
US-9,785,613 Acoustic processing unit interface for determining senone scores using a greater clock frequency than that...
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, a speech recognition system is provided....
US-9,785,612 Method and device for determining a range of a vehicle
A method for determining a range of a vehicle, the vehicle having an electric motor to supply driving power and/or to recuperate braking energy, and a weight of...
US-9,785,610 Visual display of vehicle wheel assembly for vehicle wheel service system
A vehicle wheel service system configured to present an operator with an interactive visual display of vehicle service system components and a virtual model of...
US-9,785,609 Computer architecture with a hardware accumulator reset
A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the...
US-9,785,608 Predictive, multi-layer caching architectures
Predictive, multi-layer caching architectures may be used to predict which elements a user is most likely to navigate to within a collection of elements...
US-9,785,607 In-situ die-to-die impedance estimation for high-speed serial links
A receiver includes an analog-to-digital converter (ADC) module that receives a test signal via a transmission channel and provides a time domain representation...
US-9,785,606 Systems, methods, and devices for media agnostic USB packet scheduling
Example systems, methods, and devices are disclosed for scheduling traffic by a media agnostic universal serial bus protocol adaptive layer. In one embodiment,...
US-9,785,605 Predefined static enumeration for dynamic enumeration buses
Predefined static enumeration systems and processes for dynamic enumeration buses are disclosed. In one aspect, the dynamic enumeration bus may be a...
US-9,785,604 Preset evaluation to improve input/output performance in high-speed serial interconnects
Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some...
US-9,785,603 Devices, systems, and methods of reducing chip select
Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a...
US-9,785,602 Device and method for measuring, recording and reporting fluid flow
An electronic flow instrument and method which uses the instrument for monitoring and/or controlling the production or flow of a fluid. The instrument has a...
US-9,785,601 System and method for reducing cross coupling effects
A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is...
US-9,785,600 Modular mass storage system
A system for storing data includes a rack, one or more data storage modules coupled to the rack, and one or more data control modules coupled to the rack. The...
US-9,785,599 Information processing apparatus and log output method
A storage unit stores management information including information indicative of a correspondence relation between a plurality of devices and a plurality of...
US-9,785,598 USB hubs with galvanic isolation
A universal serial bus (USB) hub includes a USB AFE circuit module, a hub core and an isolator circuit module interposed between the USB AFE circuit module and...
US-9,785,597 Mapping device addresses to physical memory addresses
A data processing system includes a main storage, an input/output memory management unit (IOMMU) coupled to the main storage, a peripheral component...
US-9,785,595 Multi-channel universal serial bus (USB) to subrate channel systems
Multi-channel universal serial bus (USB) to subrate channel systems and methods are disclosed. According to an aspect, a system includes a USB interface...
US-9,785,594 Micro server and switch device thereof
A micro server is provided. The micro server includes a plurality of computer boards, at least one switch device, and a baseboard. The plurality of computer...
US-9,785,593 Portable device with data transmission between main system and subsystem and control method therefor
A portable device provided includes a main processor, an IO processor, a channel port coupled between the main processor and the IO processor, and at least one...
US-9,785,592 High density mapping for multiple converter samples in multiple lane interface
An apparatus having a plurality of buffers, a first circuit and a second circuit is disclosed. The buffers are configured to store a plurality of frames to be...
US-9,785,591 Smartcard interface conversion device, embedded system having the same device and method for transferring data...
The present invention relates to an apparatus and a method for transferring a data signal between a smartcard interface and an interface of a processor within...
US-9,785,590 Bus auto-addressing system
The invention pertains to automatically addressing devices on a network. The controller tests each address from a list of available addresses. If the control...
US-9,785,589 Memory controller that calibrates a transmit timing offset
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal...
US-9,785,588 Methods and systems for devices with self-selecting bus decoder
Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a...
US-9,785,587 Method for executing, within a multitasking onboard system, an application timed according to a plurality of...
A method for executing an application in a multitasking system is provided. The application is composed of at least one task for which the temporal triggering...
US-9,785,586 Electronic computer and interrupt control method
An electronic computer includes a processor that executes a thread and an interrupt handler, and monitors load of the processor; and an interrupt controller...
US-9,785,585 Method for card reader to communicate with upper computer via USB channel communication and Bluetooth channel...
A method for a card reader to communicate with an upper computer comprises: initializing a card reader system and enabling an interrupt; determining an...
US-9,785,584 Data storage device and method thereof
A data storage device includes a nonvolatile memory device; a buffer memory for storing temporarily data to be transmitted from the nonvolatile memory device to...
US-9,785,583 Storage router and method for providing virtual local storage
A storage router and method for providing virtual local storage on remote storage devices to devices are provided. Devices are connected to a first transport...
US-9,785,582 Data processing architecture and data processing method
A data processing architecture includes a processor which may access a memory and fetch a command recorded in the memory, transmit the fetched command to a...
US-9,785,581 Memory distribution across multiple non-uniform memory access nodes
A system, methods, and apparatus for determining memory distribution across multiple non-uniform memory access processing nodes are disclosed. An apparatus...
US-9,785,580 Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system
A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes N machines...
US-9,785,579 Memory controller, information processing apparatus, and method of controlling memory controller
A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the...
US-9,785,578 Apparatus and method for controlling access to a memory device
An apparatus and method are provided for controlling access to a memory device. The apparatus has a pending access requests storage that is used to store access...
US-9,785,577 Kernel key handling
According to one example, a method performed by a computing system includes determining that a size of key data to be stored within a kernel memory is greater...
US-9,785,576 Hardware-assisted virtualization for implementing secure video output path
Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a...
US-9,785,575 Optimizing thin provisioning in a data storage system through selective use of multiple grain sizes
A data storage system includes a pre-cache and a plurality of storage devices across which a data storage array is distributed. In response to receipt of a...
US-9,785,574 Translation lookaside buffer that employs spacial locality
A system may include a memory that includes a plurality of pages, a processor, and a translation lookaside buffer (TLB) that includes a plurality of entries....
US-9,785,573 Systems and methods for storage of data in a virtual storage device
A system for providing data storage includes at least one virtual server comprising at least one virtual storage device; at least one physical server comprising...
US-9,785,572 Memory controller with multimodal control over memory dies
This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing...
US-9,785,571 Methods and systems for memory de-duplication
Provided are methods and systems for de-duplicating cache lines in physical memory by detecting cache line data patterns and building a link-list between...
US-9,785,570 Memory devices and modules
An embodiment includes a system, comprising: an Error Correcting Code (ECC) memory comprising a plurality of memory locations, each memory location...
US-9,785,569 Radix table translation of memory
A method includes receiving a request to access a desired block of memory. The request includes an effective address that includes an effective segment...
US-9,785,568 Cache lookup bypass in multi-level cache systems
Techniques described herein are generally related to retrieval of data in computer systems having multi-level caches. The multi-level cache may include at least...
US-9,785,567 Operand cache control techniques
Techniques are disclosed relating to per-pipeline control for an operand cache. In some embodiments, an apparatus includes a register file and multiple...
US-9,785,566 Semiconductor device, computer, and electronic device
A novel semiconductor device, a semiconductor device capable of operating at high speed, or a semiconductor device with low power consumption is provided. The...
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