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Patent # Description
US-9,785,565 System and methods for expandably wide processor instructions
Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The...
US-9,785,564 Hybrid memory with associative cache
A hybrid memory system includes a primary memory comprising a host memory space arranged as memory sectors corresponding to host logical block addresses (host...
US-9,785,563 Read command processing for data storage system based on previous writes
A read command is received from a host requesting data from a portion of a first memory of a data storage system and it is determined whether one or more...
US-9,785,562 Adjusting allocation of storage devices
Embodiments of the present invention provide methods, computer systems, and computer program products for adjusting allocation of a storage device. In one...
US-9,785,561 Integrating a flash cache into large storage systems
An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a...
US-9,785,560 Scene-isolated internet application
Computer-implemented systems, methods and apparatus are provided for rendering different scenes of an application. An application framework is provided that...
US-9,785,559 Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and...
Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an...
US-9,785,558 Mixed cache management
A mixed cache is indexed to main memory and page coloring is applied to map main memory to virtual memory. A nursery array and a mature array are indexed to...
US-9,785,557 Translation entry invalidation in a multithreaded data processing system
In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of...
US-9,785,556 Cross-die interface snoop or global observation message ordering
Methods and apparatus relating to techniques for Cross-Die Interface (CDI) snoop and/or go (or completion) message ordering are described. In one embodiment,...
US-9,785,555 Synchronizing updates of page table status indicators in a multiprocessing environment
A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page...
US-9,785,554 Synchronizing updates of page table status indicators in a multiprocessing environment
A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page...
US-9,785,553 Asynchronous cleanup after a peer-to-peer remote copy (PPRC) terminate relationship operation
For asynchronous cleanup after a peer-to-peer remote copy (PPRC) terminate relationship operation in a computing storage environment by a processor device,...
US-9,785,552 Computer system including virtual memory or cache
According to one embodiment, a computer system includes a first memory unit, a second memory unit having a data transfer rate lower than that of the first...
US-9,785,551 Memory access method, buffer scheduler and memory module
The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without...
US-9,785,550 Data storage device and operating method thereof
A data storage device includes a nonvolatile memory device including a plurality of memory areas; and a controller configured to perform a reclaim operation for...
US-9,785,549 Managing object lifetime for native/managed peers
A system that manages lifetime of an object is provided. The system analyzes references on multiple objects to determine reachability of a native peer and...
US-9,785,548 Hardware extensions for memory reclamation for concurrent data structures
A hardware-assisted mechanism may improve the performance of memory reclamation operations that employ hazard pointers. The mechanism includes hazard lookaside...
US-9,785,547 Data management apparatus and method
A data management apparatus for reducing the occurrence of garbage collection, and preventing deterioration in the performance of writing data into an SSD. The...
US-9,785,546 Methods for scheduling read commands and apparatuses using the same
A method for scheduling read commands, performed by a processing unit, including at least the following steps. Logical read commands are received from a master...
US-9,785,545 Method and apparatus for providing dual memory access to non-volatile memory
A method and system for providing a dual memory access to a non-volatile memory device using expended memory addresses are disclosed. The digital processing...
US-9,785,544 Testing a mobile application
The present invention discloses a manager, a test agent installed on a personal mobile device and methods thereof. The manager comprises: a first network...
US-9,785,543 Dual tagging between test and pods
A method of applying test routines to pods in an automated application test suite may include receiving a selection of a pod representing an operating...
US-9,785,542 Implementing edit and update functionality within a development environment used to compile test plans for...
A method for debugging test procedures for automated device testing is disclosed. The method comprises receiving a command to update at least one modified test...
US-9,785,541 System, method, and computer program for generating test reports showing business activity results and statuses
A system, method, and computer program product are provided. At least one testing project to be performed is identified, and a diagram is generated from testing...
US-9,785,540 Generic language application programming interface interpreter
Technical solutions are described for facilitating a first computer program product to communicate with a second computer program product. The first computer...
US-9,785,539 Application development via a multi-unit device
Disclosed are various embodiments for systems and methods to provide to a processor unit over a network. The processor unit may be used for testing ...
US-9,785,538 Arbitrary instruction execution from context memory
Arbitrary instruction execution from context memory. In some embodiments, an integrated circuit includes a processor core; a context management circuit coupled...
US-9,785,537 Runtime exception and bug identification within an integrated development environment
In one embodiment, a computer-implemented method includes monitoring one or more data sources resulting from execution of one or more program components. One or...
US-9,785,536 Code injection for conditional breakpoints
An apparatus for debugging operational code of a target program comprises a memory storing the operational code and a set of instructions representing a...
US-9,785,535 Multi-data analysis based proactive defect detection and resolution
Multi-data analysis based proactive defect detection and resolution may include analyzing operational data for an application to determine whether a...
US-9,785,534 Method and system for using abandonment indicator data to facilitate progress and prevent abandonment of an...
Abandonment indicator data is used to customize the user experience of an interactive software system, by monitoring and obtaining data about whether a user is...
US-9,785,533 Session template packages for automated load testing
A computer-implemented method includes scanning a clip of messages that includes message requests and message responses arranged in a sequence. The scanning is...
US-9,785,532 Performance regression manager for large scale systems
Methods comprising generating, based on a first output generated by a first execution instance of a command, a first output file specifying a value of at least...
US-9,785,531 Link speed downshifting for error determination and performance enhancements
Various embodiments for regulating link speed for performance enhancement and port diagnosis are provided. In response to identifying an amount of errors in a...
US-9,785,530 Method, device, and system for processing PCIe link fault
In a Peripheral Component Interconnect Express (PCIe) system, a first PCIe apparatus determines that at least one of lanes of a link between the first PCIe...
US-9,785,529 Lost computing resource notification
Some embodiments of a system and a method to notify applications of lost computing resources have been presented. For instance, a processing device running on a...
US-9,785,528 System and method for using data tags to track and manage tasks to provide object-to-object services
The present invention relates to a method and system that use data tags to track tasks in applications to provide Object-to-Object (OTO) services. A first...
US-9,785,527 Methods, systems, and computer readable media for emulating virtualization resources
Methods, systems, and computer readable media for emulating virtualization resources are disclosed. According to one method, the method occurs at a computing...
US-9,785,526 Automated generation of a test class pre-header from an interactive graphical user interface
A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining information concerning a test class using a...
US-9,785,525 High availability failover manager
A high availability (HA) failover manager maintains data availability of one or more input/output (I/O) resources in a cluster by ensuring that each I/O...
US-9,785,523 Managing replicated virtual storage at recovery sites
Techniques involving replication of storage are described. A representative technique includes apparatuses and methods for receiving replicated virtual storage...
US-9,785,522 Adaptive datacenter topology for distributed frameworks job control through network awareness
Systems, methods, and computer program products to perform an operation comprising receiving a priority of a distributed computing job, an intermediate traffic...
US-9,785,521 Fault tolerant architecture for distributed computing systems
Disclosed here is a fault tolerant architecture suitable for use with any distributed computing system. A fault tolerant architecture may include any suitable...
US-9,785,520 Computer system, storage apparatus and control method
A computer system has a storage system including a first port and a second port, and a relay apparatus which couples the first port to an initiator apparatus....
US-9,785,519 Driver switch for device error recovery for assigned devices
An error recovery system includes a memory, a processor in communication with the memory, a primary device, a backup device, a hypervisor executing on the...
US-9,785,518 Multi-threaded transaction log for primary and restore/intelligence
A unified system provides primary storage and in-line analytics-based data protection. Additional data intelligence and analytics gathered on protected data and...
US-9,785,517 Rebuilding damaged areas of a volume table using a volume data set
Provided a computer program product, system, and method for rebuilding damaged areas of a volume table using a volume data set for managing data sets assigned...
US-9,785,516 Method and system to remove a service from a distributed database system
A method, medium, and system to receive a request to remove a service of an instance of a distributed database system; redistribute data of the service to be...
US-9,785,515 Directed backup for massively parallel processing databases
Creating a data backup of data on a first computer system to restore to a second computer system, each of the first and second computer system including one or...
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