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Patent # Description
US-9,793,947 Scalable protocol for large WSNs having low duty cycle end nodes
A method and system are described for providing a wireless sensor network between a main node and a plurality of nodes, the nodes associated with sensors. The...
US-9,793,946 Rake receiver and receiving method thereof
A disclosure of the present specification provides a rake receiver. The rake receiver may comprise: an oscillator; a radio frequency integrated circuit (RFIC)...
US-9,793,945 Determination of channel condition indication
A method is provided of a wireless communication device operating in connection with a cellular communication system providing a serving cell and one or more...
US-9,793,944 System and apparatus for decoding tree-based messages
A system and techniques for decoding a message received over a communication channel comprises a receiver for receiving an encoded message. A sorting module is...
US-9,793,943 Duplexer-less transceiver and communication apparatus
A duplexer-less transceiver arrangement is disclosed. The transceiver comprises a receiver configured for frequency-division duplex communication with a...
US-9,793,942 Systems and methods for a switchless radio front end
A radio circuit, comprises an antenna; a differential power amplifier, comprising differential transmit inputs and differential transmit outputs, configured to...
US-9,793,941 Apparatus to assist a user with holding a mobile device
An apparatus that facilitates one-handed use of a mobile device has a finger brace coupled a plurality of flexible lengths. At least one of the flexible lengths...
US-9,793,940 Cover for mobile device
A cover for a mobile device includes a cover body to be mounted on the mobile device, an operation portion provided on the cover body and capable of receiving...
US-9,793,939 Automatic self-protection for a portable electronic device
Provided are techniques for automatically protecting portable and wearable electronic devices from potential hazards by predicting when such hazards may occur....
US-9,793,938 Intermediate-frequency analogue-to-digital conversion device
Provided is an intermediate-frequency analog-to-digital conversion device, including: a gain attenuation module, a gain amplification module, a filter and an...
US-9,793,937 Apparatus and method for filtering wireless signals
An apparatus and method are described for filtering wireless signals. For example, one embodiment of the invention comprises: one or more radios to receive a...
US-9,793,936 Flexible multi-channel wireless audio receiver system
A flexible multi-channel diversity wireless audio receiver system for routing, processing, and combining multiple radio frequency (RF) signals containing audio...
US-9,793,935 Multi-mixer system and method for reducing interference within multi-mixer system
A multi-mixer system includes an amplifier module and a plurality of channels. The amplifier module is arranged for receiving signals from an antenna or antenna...
US-9,793,934 Wireless receiver
A wireless receiver includes an RF muting circuit that opens and closes a signal line of a demodulated signal according to a received carrier strength level, a...
US-9,793,933 System and method for digital interference cancellation
A system and method for receiving a signal, comprising an input adapted to receive a radio frequency signal having a strong interferer; a signal generator,...
US-9,793,932 Systems and methods for a predistortion linearizer with frequency compensation
An analog predistortion linearizer system with dynamic frequency compensation for automatically adjusting predistortion characteristics based on a detected...
US-9,793,931 Method and apparatus for detecting transmitters for a white space device
The invention relates to a wireless home gateway apparatus and methods of wirelessly delivering audio and/or video programs between a home gateway and a client...
US-9,793,930 Using LTE-A transmitters and carrier aggregation in borehole communication
In a method, an apparatus and a system for data transmission, a plurality of transmitters are provided, which operate according to a communications standard for...
US-9,793,929 Data packing for compression-enabled storage systems
A computer-implemented method, according to one embodiment, includes: repeating the following sequence at least until a page stripe of a memory cache has at...
US-9,793,928 Method and device for measuring the current signal-to-noise ratio when decoding LDPC codes
A method for measuring a signal-to-noise ratio when decoding Low Density Parity Check (LDPC) codes is provided. The method includes receiving from an input of a...
US-9,793,927 Storage systems with adaptive erasure code generation
Apparatuses, methods and storage medium associated with generating erasure codes for data to be stored in a storage system. In embodiments, a method may include...
US-9,793,926 Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
US-9,793,925 Data processing device and data processing method
In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 with a...
US-9,793,924 Method and system for estimating an expectation of forward error correction decoder convergence
A forward error correction decoder and method of decoding a codeword is provided. The decoder comprises a convergence processor for estimating an expectation of...
US-9,793,923 LDPC post-processor architecture and method for low error floor conditions
Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving...
US-9,793,922 Repair-optimal parity code
Techniques for generating parities and repairing data erasures using repair-optimal parities are disclosed. The system includes an encoding module, which...
US-9,793,921 Methods and apparatus for unified significance map coding
Methods and apparatus are provided for unified significance map coding. An apparatus includes a video encoder for encoding transform coefficients for at least a...
US-9,793,920 Computer-readable recording medium, encoding device, and encoding method
The encoding device 100 extracts, when encoding a target file by using a static dictionary unit 121 and a dynamic dictionary unit 122, a registered word...
US-9,793,919 Compression of frequent data values across narrow links
Systems, apparatuses, and methods for compression of frequent data values across narrow links are disclosed. In one embodiment, a system includes a processor, a...
US-9,793,918 Memory compression operable for non-contiguous write/read addresses
A digital data storage and retrieval system. The system has a first memory for storing a plurality of data quantities, and each data quantity, in the plurality...
US-9,793,917 Method and apparatus for adjusting a bandwidth of a sigma delta converter
A method and apparatus for adjusting a bandwidth of a sigma delta converter by adjusting a reference voltage provided to the sigma delta converter. The...
US-9,793,916 Level shifter, digital-to-analog converter, and buffer amplifier, and source driver and electronic device...
A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The...
US-9,793,915 Successive approximation analog-to-digital converter (ADC) with dynamic search algorithm
Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a...
US-9,793,914 Analog-to-digital converter, electronic device, and method of controlling analog-to-digital converter
An analog signal is accurately converted into a digital signal. An oscillator generates an oscillation signal having a cycle that depends on a signal level of...
US-9,793,913 Single-flux-quantum probabilistic digitizer
A probabilistic digitizer for extracting information from a Josephson comparator is disclosed. The digitizer uses statistical methods to aggregate over a set of...
US-9,793,912 Analog-to-digital conversion circuitry with real-time adjusted gain and resolution
Analog-to-digital conversion circuitry for generating a digital output signal is disclosed comprising a sample-and-hold circuit comprising an adjustable sample...
US-9,793,911 Semiconductor device including analog to digital conversion circuit
An object of the present invention is to shorten time required for detecting disconnection in an input terminal of an A/D conversion circuit. A semiconductor...
US-9,793,910 Time-interleaved ADCs with programmable phases
A time-interleaved analog-to-digital converter (ADC) uses M analog-to-digital converters to sample an analog input signal to produce digital outputs. The M...
US-9,793,909 Analog-to-digital converter, including synchronized clocks, image sensor including the same and method of...
An image sensor includes a pixel array, a plurality of comparators, a plurality of counters and a plurality of synchronization circuits. The pixel array...
US-9,793,908 Protection circuits for tunable resistor at continuous-time ADC input
Continuous-time analog-to-digital converters (ADCs) such as continuous-time delta-sigma ADCs and continuous-time pipeline ADCs, has input resistor structure at...
US-9,793,907 Resonator, phase-locked loop, and semiconductor integrated circuit device
A resonator is supplied with voltage from a constant-voltage source, and the constant-voltage source outputs output voltage adjusted by a voltage adjustment...
US-9,793,906 Range and process compensation for a digital phase locked loop (PLL) or frequency locked loop (FLL) circuit
A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal...
US-9,793,905 Semiconductor device
An object of the present invention is to provide a semiconductor device including an oscillator circuit including a circuit between inverters. In the circuit, a...
US-9,793,904 System and method of noise correcting PLL frequency synthesizers
An improved noise-corrected phase-locked loop frequency synthesizer configured to reduce noise, such as phase noise and spurious signals, without the use of...
US-9,793,903 Device and method for recovering clock and data
A clock and data recovery device includes a data sampling module, a phase detection circuit, a frequency estimator, a clock generation module, and a data...
US-9,793,902 Reference-less clock and data recovery circuit
Embodiments herein describe a reference-less CDR circuit that receives electrical signals that may have been transmitted along either an electrical or optical...
US-9,793,901 Integrated circuit
An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to...
US-9,793,900 Distributed multi-phase clock generator having coupled delay-locked loops
Multiple, distributed, clock generating delay-locked loop (DLL) elements are interconnected/coupled in such a way as to reduce the amount of phase error present...
US-9,793,899 Mitigation of single event latchup
The disclosed IC includes a load circuit and a temperature sensor circuit. The temperature sensor circuit measures temperature of the IC and stores temperature...
US-9,793,898 Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same
An integrated circuit comprising a plurality of switch matrices wherein the plurality of switch matrices are arranged in stages including (i) a first stage,...
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