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Patent # Description
US-9,793,283 High conductivity channel for 3D memory
Disclosed herein is a 3D memory with vertical NAND strings, and method for fabricating the same. Each vertical NAND string has a source side select transistor...
US-9,793,282 Floating gate memory cells in vertical memory
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A...
US-9,793,281 Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate,...
A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming...
US-9,793,280 Integration of split gate flash memory array and logic devices
A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area,...
US-9,793,279 Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing
A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between,...
US-9,793,278 Structure of memory cell with asymmetric cell structure and method for fabricating the same
A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to...
US-9,793,277 Method of maintaining the state of semiconductor memory having electrically floating body transistor
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to...
US-9,793,276 Semiconductor device having transistor and capacitor
A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times...
US-9,793,275 Multilayer circuit
A multilayer circuit (400) includes a base layer (205) which has a number of base vias (247, 415), a first overlying layer (215) formed on the base layer (205)...
US-9,793,274 CMOS transistors including gate spacers of the same thickness
A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is ...
US-9,793,273 Fin-based semiconductor device including a metal gate diffusion break structure with a conformal dielectric layer
The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more...
US-9,793,272 Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and...
A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an...
US-9,793,271 Semiconductor device with different fin pitches
A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second...
US-9,793,270 Forming gates with varying length using sidewall image transfer
Semiconductor devices and methods of forming the same include forming mandrels on a first region and a second region of a gate layer. First spacers are formed...
US-9,793,269 Semiconductor device and method of manufacture
In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first...
US-9,793,268 Method and structure for gap filling improvement
The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin...
US-9,793,267 Semiconductor device having gate structure with reduced threshold voltage and method for manufacturing the same
A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at...
US-9,793,266 Semiconductor device
An influence of a gate interference is suppressed and a reverse recovery property of a diode is improved. A diode includes a diode region located between the...
US-9,793,265 Semiconductor device including Schottky barrier diode and power MOSFETs and a manufacturing method of the same
In a non-insulated DC-DC converter having a circuit in which a power MOS.cndot.FET high-side switch and a power MOS.cndot.FET low-side switch are connected in...
US-9,793,264 Vertical metal insulator metal capacitor having a high-K dielectric material
A vertical metal-insulator-metal (MIM) capacitor is formed within multiple layers of a multi-level metal interconnect system of a chip. The vertical MIM...
US-9,793,263 Digital alloy FinFET co-integrated with passive resistor with good temperature coefficient
A method for integrating fin field effect transistors (FinFETs) and resistors on a common substrate is provided. By employing a digital alloy as a channel...
US-9,793,262 Fin diode with increased junction area
A method includes forming a first plurality of fins having a first width in a first region of a semiconductor substrate. A second plurality of fins having a...
US-9,793,261 Power semiconductor device
A power semiconductor device includes: a first MOSFET having a first conductivity type including a first source, a first drain, and a first gate; a second...
US-9,793,260 System and method for a switch having a normally-on transistor and a normally-off transistor
In accordance with an embodiment, a method includes conducting a reverse current through a first switch that includes a normally-on transistor coupled in series...
US-9,793,259 Integrated semiconductor device
A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.
US-9,793,258 Electrostatic discharge device
An electrostatic discharge device includes a substrate. A deep doped well of a first conductive type is disposed in the substrate. A drain doped well of the...
US-9,793,257 Electrostatic discharge protection device having an adjustable triggering threshold
An electrostatic discharge protection device includes first and second diodes series-connected between first and second connection terminals. A third connection...
US-9,793,256 Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated...
US-9,793,255 Power semiconductor device including a cooling material
A power semiconductor device includes a wiring structure adjoining at least one side of a semiconductor body and comprising at least one electrically conductive...
US-9,793,254 TVS structures for high surge and low capacitance
A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device...
US-9,793,253 Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including...
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells...
US-9,793,252 Method of integrating inorganic light emitting diode with oxide thin film transistor for display applications
A method of fabricating an active matrix display is disclosed in which one or more oxide thin film transistors is monolithically integrated with an inorganic...
US-9,793,251 Semiconductor package and manufacturing method thereof
Disclosed herein is a semiconductor package in which a semiconductor chip and a mounting device are packaged together. The semiconductor package includes a...
US-9,793,250 Package board, method for manufacturing the same and package on package having the same
There are provided a package board, a method for manufacturing the same, and a package on package having the same. The package board according to an exemplary...
US-9,793,249 Light emitting device and light unit having the same
A light emitting device is provided. The light emitting device may include a body, first and second lead frames coupled to the body, a first light emitting chip...
US-9,793,248 Light emitting device
A light emitting device includes a substrate, a plurality of micro light emitting chips and a plurality of conductive bumps. The substrate has a plurality of...
US-9,793,247 Solid state lighting component
An LED component according to the present invention comprising an array of LED chips mounted on a submount with the LED chips capable of emitting light in...
US-9,793,246 Pop devices and methods of forming the same
PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package...
US-9,793,245 Semiconductor device and method of manufacture
A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two...
US-9,793,244 Scalable package architecture and associated techniques and configurations
Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and...
US-9,793,243 Buffer layer(s) on a stacked structure having a via
A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and...
US-9,793,242 Packages with die stack including exposed molding underfill
A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package...
US-9,793,241 Printed wiring board
A printed wiring board includes a lowermost resin insulating layer, a first conductor layer formed on a first surface of the lowermost resin insulating layer, a...
US-9,793,240 Multiple die layout for facilitating the combining of an individual die into a single die
An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each...
US-9,793,239 Semiconductor workpiece with selective backside metallization
Various semiconductor workpieces with selective backside metallizations and methods of making the same are disclosed. In one aspect, a method of manufacturing...
US-9,793,238 Copper wire and electrode joining method and joint structure
With this copper wire joining method, a rubbed portion on which a coating remains between an electrode and a core wire is formed on the electrode. Then, after a...
US-9,793,237 Hollow-cavity flip-chip package with reinforced interconnects and process for making the same
The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed...
US-9,793,236 Wire-bonding apparatus and method of manufacturing semiconductor device
Provided is a wire-bonding apparatus (10) including: a capillary (28) through which a wire (30) inserted; and a controller (80). The controller (80) is...
US-9,793,235 Semiconductor package having a bump bonding structure
A semiconductor package may be provided. The semiconductor package may include a substrate having a first surface over which bond fingers are arranged, the...
US-9,793,234 Chip package and manufacturing method thereof
A chip package includes a first chip and a second chip. The first chip includes a first substrate having a first surface and a second surface opposite to the...
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