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Patent # Description
US-9,792,266 Content synchronization across devices
Techniques and solutions are described for content synchronization across devices. A web page currently being viewed at a first device associated with a user...
US-9,792,265 Systems and methods for hosted applications
In one embodiment, a computing device configured to execute a hosted application includes a processor and storage, where an operating system is installed on the...
US-9,792,264 Inheritance of rules across hierarchical levels
Rules, such as condition-action rules, are configured at different levels of a hierarchy. Rules created at a higher hierarchical level are automatically...
US-9,792,263 Human input to relate separate scanned objects
A method for managing a hardcopy document (HD). The method includes: obtaining an image of the HD; identifying, within the image, a plurality of linking labels...
US-9,792,262 Client-side web service provider
To facilitate client access to web services, a server may be configured to package or bundle a function call for a web service with associated information. The...
US-9,792,261 Medical image display apparatus, medical image display method, and recording medium
A medical image display apparatus determines a priority order of each of medical image data based on a display direction of a body model and an imaging...
US-9,792,260 Visual screen indicator
Embodiments of the present disclosure provide systems and method for viewing electronic documents. Briefly described, one embodiment of the system, among...
US-9,792,259 Systems and/or methods for interactive exploration of dependencies in streaming data
Certain example embodiments allow for the continuous discovery and analysis of dependencies in a multidimensional event stream in which various regression...
US-9,792,258 Methods for determining well characteristics and pore architecture utilizing conventional well logs
Provided are methods, computer readable medium, apparatus, and program code for determining well characteristics and pore architecture for a hydrocarbon well...
US-9,792,257 Audio signal processing method and encoder
An embodiment of the present invention discloses a data processing method, including: twiddling input data, so as to obtain twiddled data; pre-rotating the...
US-9,792,256 Method and device for monitoring an actuator system
A method for monitoring an actuator in a physical system, including: providing a computer model that describes the actuator, the behavior of the actuator being...
US-9,792,255 Electronic state calculation method, electronic state calculation device, and recording medium
A method of calculating an electronic state of a material by using a calculation device, wherein the calculation device sets a set containing, as elements, a...
US-9,792,254 Computing intersection cardinality
A computer-implemented method for computing an intersection or an intersection cardinality of each pair of a set in a first list of a plurality of sets and a...
US-9,792,253 Sensor device, sensor management system, method for controlling sensor device, and computer-readable recording...
A sensor device has a difference calculation unit that calculates the difference between a predetermined threshold and a current measured value measured by a...
US-9,792,252 Incorporating a spatial array into one or more programmable processor cores
Functional units disposed in one or more processor cores are communicatively coupled using both a shared bypass network and a switched network. The shared...
US-9,792,251 Array of processor core circuits with reversible tiers
Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and...
US-9,792,250 System on chip module configured for event-driven architecture
A system on chip (SoC) module is described herein, wherein the SoC modules comprise a processor subsystem and a hardware logic subsystem. The processor...
US-9,792,249 Node card utilizing a same connector to communicate pluralities of signals
A system and method for provisioning of modular compute resources within a system design are provided. In one embodiment, a node card or a system board may be...
US-9,792,248 Fast read/write between networked computers via RDMA-based RPC requests
An "RDMA-Based RPC Request System" combines the concepts of RPC and RDMA in a way that can be implemented on commodity networking communications hardware, e.g.,...
US-9,792,247 Systems and methods for chip to chip communication
Systems and methods for chip to chip communication are disclosed. In an exemplary aspect, a chip to chip link comprises a master device having a data...
US-9,792,246 Lower-power scrambling with improved signal integrity
An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling...
US-9,792,245 Peripheral component interconnect express (PCIe) devices with efficient memory mapping by remapping a plurality...
Embodiments herein provide for efficient memory mapping in a PCIe device when a host changes memory allocations in the device. One PCIe device comprises a...
US-9,792,244 Multiple processor architecture with flexible external input/output interface
A multiple processor architecture with flexible external input/output interface is provided. In one embodiment, an open flexible processor architecture avionics...
US-9,792,243 Computer architecture to provide flexibility and/or scalability
Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot...
US-9,792,242 Systems and methods for non-unicast/destination lookup fail (DLF) load balancing
Aspects of the present invention include a port extender environment using the port extenders to dynamically select a data path. In embodiments of the present...
US-9,792,241 Interface for bridging out-of-band information from a downstream communication link to an upstream...
A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A...
US-9,792,240 Method for dynamic configuration of a PCIE slot device for single or multi root ability
A method and an information handling system (IHS) selectively configures a peripheral component interconnect express (PCIe) device with single or multiple root...
US-9,792,239 Tablet case with switching circuit for on-the-go USB port
A tablet cover (100) and circuitry (400) provide for convenient connection of a tablet (105) or other personal electronic device to additional memory,...
US-9,792,238 Method and apparatus for configuring a cluster system, and system
Embodiments of the present invention disclose a method and apparatus for processing a cluster in a cluster system, and a cluster system, relate to the field of...
US-9,792,237 Information processing apparatus capable of connecting with peripheral device and terminal apparatus capable of...
According to an embodiment, an information processing apparatus includes a communication control module and a peripheral device control module. The...
US-9,792,235 Optimized credit return mechanism for packet sends
Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a...
US-9,792,234 Secure direct memory access
Examples are disclosed for establishing a secure destination address range responsive to initiation of a direct memory access (DMA) operation. The examples also...
US-9,792,233 Techniques for escalating interrupts in a data processing system to a higher software stack level
A technique for escalating interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification...
US-9,792,232 Techniques for queueing interrupts in a data processing system
A method of handling interrupts in a data processing system includes maintaining a first interrupt destination buffer (IDB) for a first interrupt handler...
US-9,792,231 Computer system for managing I/O metric information by identifying one or more outliers and comparing set of...
Systems and methods are described for dynamically detecting outliers in a set of input/output (I/O) metrics collected and aggregated by a storage volume...
US-9,792,230 Data input circuit of semiconductor apparatus
A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a...
US-9,792,229 Protecting a memory
In an embodiment, a processor includes: at least one core to execute instructions; and a memory protection logic to encrypt data to be stored to a memory...
US-9,792,228 Enhancing lifetime of non-volatile cache by injecting random replacement policy
A method, a system and a computer-readable medium for writing to a non-volatile cache memory are provided. The method maintains a write count associated with a...
US-9,792,227 Heterogeneous unified memory
Inventive aspects include a heterogeneous unified memory section, which includes an extended unified memory space across a plurality of physical heterogeneous...
US-9,792,226 Predictive cache replacement
Systems and methods for predictive cache replacement policies are provided. In particular, some embodiments dynamically capture and predict access patterns of...
US-9,792,225 Host and computer system having the same
A host includes a cache including a plurality of cache lines, a command descriptor list configured to store a command transmitted from one of the plurality of...
US-9,792,224 Reducing latency by persisting data relationships in relation to corresponding data in persistent memory
A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a...
US-9,792,223 Processor including load EPT instruction
A processor including an extended page table (EPT) translation mechanism that is enabled for virtualization, and a load EPT instruction. When executed by the...
US-9,792,222 Validating virtual address translation by virtual machine monitor utilizing address validation structure to...
Systems and methods for validating virtual address translation. An example processing system comprises: a processing core to execute a first application...
US-9,792,221 System and method for improving performance of read/write operations from a persistent memory device
A memory unit and method are disclosed. The memory unit comprises: at least one controller interfaced with at least one corresponding persistent memory device...
US-9,792,220 Microcontroller for memory management unit
One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a...
US-9,792,219 Nonvolatile memory systems with embedded fast read and write memories
A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are...
US-9,792,218 Data storage methods and apparatuses for reducing the number of writes to flash-based storage
Methods and apparatuses are provided for reducing the number of write operations to a flash-based storage system that stores and replaces data. The storage...
US-9,792,217 Methods and systems for normalizing a read-write cache allocation pool for virtual desktop infrastructure workloads
Methods and systems for normalizing a read-write cache allocation pool for virtual desktop infrastructure (VDI) workloads are disclosed. The method includes...
US-9,792,216 System and method of determining memory ownership on cache line basis for detecting self-modifying code...
A system and method for determining memory ownership on a cache line basis for detecting self-modifying code with instructions that overlap cache line...
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