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Patent # Description
US-9,799,685 Semiconductor device
Provided is a semiconductor device suitable for miniaturization and higher density. The semiconductor device includes a first transistor, a second transistor...
US-9,799,684 Liquid crystal display
A liquid crystal display includes a first substrate, a gate line and a data line disposed on the first substrate, a first thin film transistor and a second thin...
US-9,799,683 Array substrate, preparation method thereof and display device
The present invention provides an array substrate, a preparation method thereof and a display device. The array substrate includes at least one thin film...
US-9,799,682 Method for manufacturing semiconductor device
An object is to provide a manufacturing method of a semiconductor device in which a defect in characteristics due to a crack occurring in a semiconductor device...
US-9,799,681 Panel structures of flat displays and manufacturing methods
The present disclosure discloses a panel structure of flat displays and the manufacturing method thereof. The panel structure includes a first signal line, a...
US-9,799,680 TFT array substrate, display panel, and TFT structure
A TFT array substrate includes a plurality of scan lines, a plurality of date lines, a plurality of pixels, a first TFT, and a second TFT. The number of scan...
US-9,799,679 Thin film transistor array substrate, its manufacturing method and display device
The present disclosure provides a thin film transistor (TFT) array substrate, its manufacturing method and a display device. The method includes steps of:...
US-9,799,678 Manufacturing method of thin film and metal line for display using the same, thin film transistor array panel,...
A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of...
US-9,799,677 Structure of dual gate oxide semiconductor TFT substrate
A dual gate oxide semiconductor thin-film transistor (TFT) substrate includes a substrate; a bottom gate positioned on the substrate; a bottom gate isolation...
US-9,799,676 Semiconductor device, FinFET transistor and fabrication method thereof
The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor...
US-9,799,675 Strain engineering in back end of the line
A semiconductor device including at least one semiconductor device on a first surface of a dielectric layer, and at least one stressor structure having an...
US-9,799,674 Semiconductor devices including field effect transistors
A semiconductor device includes a first device isolation layer defining active regions spaced apart from each other along a first direction on a substrate,...
US-9,799,673 Semiconductor device and method of manufacturing the same
Disclosed is a method of manufacturing a semiconductor device, including: forming a stacked structure including first material layers and second material layers...
US-9,799,672 Memory device having cell over periphery (COP) structure, memory package and method of manufacturing the same
A memory device includes a semiconductor substrate, a peripheral circuit formed on a top surface of the semiconductor substrate, a lower insulation layer...
US-9,799,671 Three-dimensional integration schemes for reducing fluorine-induced electrical shorts
Dielectric degradation and electrical shorts due to fluorine radical generation from metallic electrically conductive lines in a three-dimensional memory device...
US-9,799,670 Three dimensional NAND device containing dielectric pillars for a buried source line and method of making thereof
A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of...
US-9,799,669 Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device
A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer...
US-9,799,668 Memory cell having isolated charge sites and method of fabricating same
Memory cells having isolated charge sites and methods of fabricating memory cells having isolated charge sites are described. In an example, a nonvolatile...
US-9,799,667 Method of manufacturing a semiconductor device
A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate,...
US-9,799,666 Semiconductor device
At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing...
US-9,799,665 Method for forming semiconductor device structure
A method for forming a semiconductor device structure is provided. The method includes forming a mask layer over a substrate. The method includes forming a...
US-9,799,664 Flash memory devices
The present application provides a flash memory device. The flash memory device includes a semiconductor substrate; and a plurality of tunnel oxide layers...
US-9,799,663 Stacked bit line dual word line nonvolatile memory
An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level...
US-9,799,662 Antifuse-type one time programming memory cell and array structure with same
An antifuse-type OTP memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are...
US-9,799,661 SRAM bitcell structures facilitating biasing of pull-down transistors
Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a...
US-9,799,660 Stable and reliable FinFET SRAM with improved beta ratio
Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin...
US-9,799,659 Semiconductor device having air gap, a method for manufacturing the same, a memory cell having the same and an...
A semiconductor device may include: a semiconductor substrate comprising a plurality of active regions and a device isolation region for isolating the plurality...
US-9,799,658 Methods of forming capacitors
A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support...
US-9,799,656 Semiconductor device having a gate stack with tunable work function
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first...
US-9,799,655 Flipped vertical field-effect-transistor
Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an...
US-9,799,654 FET trench dipole formation
A semiconductor structure includes a layered dipole structure formed upon a fin sidewall within a fin trench. The layered dipole structure includes a dipole...
US-9,799,653 Wafer structure for electronic integrated circuit manufacturing
A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device...
US-9,799,652 Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of...
Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded...
US-9,799,651 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer....
US-9,799,650 Semiconductor layout structure
A semiconductor layout structure includes at least a first signal line and a pair of Vss lines. The first signal line and the pair of Vss lines are extended...
US-9,799,649 Semiconductor device and manufacturing method thereof
A semiconductor device includes at least one semiconductor fin, a gate electrode, at least one gate spacer, and a gate dielectric. The semiconductor fin...
US-9,799,648 Semiconductor device
A semiconductor device of the present invention includes: an IGBT including an emitter layer on a first main surface side of a semiconductor substrate and a...
US-9,799,647 Integrated device with P-I-N diodes and vertical field effect transistors
An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second...
US-9,799,646 Cascode configured semiconductor component
In accordance with an embodiment, semiconductor component includes a compound semiconductor material based semiconductor device coupled to a silicon based...
US-9,799,645 Field effect transistor (FET) structure with integrated gate connected diodes
A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect...
US-9,799,644 FinFET and transistors with resistors and protection against electrostatic discharge (ESD)
A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each...
US-9,799,643 Gate voltage control for III-nitride transistors
A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor...
US-9,799,642 Array substrate, display device and manufacturing method of array substrate
Embodiments of the invention provide an array substrate, a display device and a manufacturing method of the array substrate. The array substrate comprises a...
US-9,799,641 Electrostatic discharge protection device and electronic device having the same
In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each...
US-9,799,640 Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with...
An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain...
US-9,799,639 Power gating for three dimensional integrated circuits (3DIC)
Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure....
US-9,799,637 Semiconductor package with lid having lid conductive structure
The present disclosure relates to a semiconductor package with a lid that includes a lid conductive structure. The semiconductor package includes a substrate...
US-9,799,636 Packaged devices with multiple planes of embedded electronic devices
A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The...
US-9,799,635 Light-emitting apparatus
Provided is a light-emitting apparatus including a substrate, first and second pairs of terminals, each pair including two terminals disposed at two opposed...
US-9,799,634 Display device using semiconductor light emitting device
The present disclosure relates to a display device, and more particularly, to a display device using a semiconductor light emitting device. Such a display...
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