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Patent # Description
US-9,799,633 Semiconductor light source with a first and a second LED chip and a first and a second fluorescent substance
A semiconductor light source comprising first and second light-emitting diode chips; and a conversion element containing a first phosphor and a second phosphor,...
US-9,799,632 Method for aligning micro-electronic components
Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced...
US-9,799,631 Semiconductor packaging structure and method
A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A...
US-9,799,630 Integrated electronic device with transceiving antenna and magnetic interconnection
An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface,...
US-9,799,629 Integrated circuit dies with through-die vias
Aspects of the disclosure are directed to integrated circuit dies and their manufacture. In accordance with one or more embodiments, a plurality of integrated...
US-9,799,628 Stacked package configurations and methods of making the same
Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first...
US-9,799,627 Semiconductor package structure and method
In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is...
US-9,799,626 Semiconductor packages and other circuit modules with porous and non-porous stabilizing layers
Integrated circuits (ICs 110) are attached to a wafer (120W). A stabilization layer (404) is formed over the wafer to strengthen the structure for further...
US-9,799,625 Semiconductor structure and manufacturing method thereof
A method of manufacturing a semiconductor structure, comprising: receiving a first substrate including a first surface, a second surface opposite to the first...
US-9,799,624 Wire bonding method and wire bonding structure
A wire bonding method includes steps of: forming a Free Air Ball (FAB) at an end of a metal wire; pressing the FAB onto a flat surface of a workpiece to deform...
US-9,799,623 Semiconductor package with conductive clip
A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can,...
US-9,799,622 High density film for IC package
The present invention discloses a high density film for IC package. The process comprises: a redistribution layer is fabricated following IC design rule, with a...
US-9,799,621 Semiconductor device and method of forming duplex plated bump-on-lead pad over substrate for finer pitch...
A semiconductor device has a substrate. A conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An...
US-9,799,620 Warpage reduction and adhesion improvement of semiconductor die package
A method of forming a die package includes forming a conductive column over a first side of a carrier, attaching a semiconductor die to the first side of the...
US-9,799,619 Electronic device having a redistribution area
An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper...
US-9,799,618 Mixed UBM and mixed pitch on a single die
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and...
US-9,799,617 Methods for repackaging copper wire-bonded microelectronic die
Methods for repacking copper wire bonded microelectronic die (that is, die having bond pads bonded to copper wire bonds) are provided. In one embodiment, the...
US-9,799,616 Package substrate with double sided fine line RDL
A package substrate has a sandwiched redistribution layers is disclosed. A middle redistribution layer functions as a core redistribution layer sandwiched by a...
US-9,799,615 Package structures having height-adjusted molding members and methods of forming the same
Package structures and methods of forming the same are disclosed. A package structure includes a die, a molding member and a redistribution circuit structure....
US-9,799,614 Calibration kits for RF passive devices
A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric...
US-9,799,613 Lead frame device
A lead frame device includes a metallic outer frame member, a lead frame package preform, and an encapsulant. The metallic outer frame member includes a pair of...
US-9,799,612 Semiconductor device and manufacturing method of the same
A semiconductor device includes a substrate, a laminated wiring layer unit, a nitride film disposed on the laminated wiring layer unit, a semiconductor element...
US-9,799,611 Semiconductor device including semiconductor chips mounted over both surfaces of substrate
A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of...
US-9,799,610 Plurality of stiffeners with thickness variation
Creating surface variations on a stiffener in a stack reduces inter-stiffener sticking and stiffener stack tilt in pick and place media. The surface variations...
US-9,799,609 Semiconductor device and a method of manufacturing the same
To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark....
US-9,799,608 Semiconductor device and method for manufacturing the same
A semiconductor device includes a monocrystalline substrate of a material which does not have a liquid phase at atmospheric pressure, and an identification mark...
US-9,799,607 Semiconductor device and method of manufacturing the same
A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions...
US-9,799,606 Semiconductor device and method of fabricating the same
A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first...
US-9,799,605 Advanced copper interconnects with hybrid microstructure
A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the...
US-9,799,604 Semiconductor device having structure for improving voltage drop and device including the same
A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers...
US-9,799,603 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first...
US-9,799,602 Integrated circuit having a staggered fishbone power network
An integrated circuit includes: a first spine formed on a first conductive layer of the integrated circuit, the spine runs in a first direction; a first...
US-9,799,601 Fuse elements and methods for forming the same
A fuse element includes a metal layer disposed on a substrate. The metal layer includes an intermediate segment, a first block and a second block. The first...
US-9,799,600 Nickel-silicon fuse for FinFET structures
Semiconductor fuses and methods of forming the same include forming a dummy gate on a semiconductor fin. A dielectric layer is formed around the dummy gate. The...
US-9,799,598 Method for producing an electronic chip support, chip support and set of such supports
Method for producing at least one electronic chip support, from a plate that includes a first face intended to be in contact with a chip reader, a second face,...
US-9,799,597 Semiconductor package
According to one embodiment, a semiconductor package includes a first substrate, first conductive layers, first semiconductor chips, a second conductive layer,...
US-9,799,596 Wiring substrate and semiconductor device
A wiring substrate includes a core substrate and a cavity extending through the core substrate. The cavity has a planar shape that is rectangular, and includes...
US-9,799,595 Careless wiring substrate having an insulation layer with a bulged covering portion and semiconductor device...
A wiring substrate is provided with a wiring pattern including a pad and a circuit pattern. The pad is formed in a mounting region where an electronic component...
US-9,799,594 Microstructure, multilayer wiring board, semiconductor package and microstructure manufacturing method
The present invention is to provide a microstructure capable of improving the withstand voltage of an insulating substrate while securing fine conductive paths,...
US-9,799,593 Semiconductor package substrate having an interfacial layer
Semiconductor package substrates and methods of forming semiconductor package substrates are described. In an example, a semiconductor package substrate...
US-9,799,592 Semicondutor device with through-silicon via-less deep wells
Methods and systems for a semiconductor device with through-silicon via-less deep wells are disclosed and may include forming a mask pattern on a silicon...
US-9,799,591 Semiconductor packages including thermal blocks
A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom...
US-9,799,590 Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in...
A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor...
US-9,799,589 Integrated circuit packaging system with a grid array with a leadframe and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: forming a conductive trace having a terminal end and a circuit end; forming a...
US-9,799,588 Chip package and manufacturing method thereof
A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate...
US-9,799,587 Semiconductor device
A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode,...
US-9,799,586 Dual power converter package
A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control...
US-9,799,585 Method for forming a case for an electronic device and manufactured case structure for electronic device
A method for forming a case for an electronic device and a manufactured case structure for an electronic device are provided. The method for forming a case for...
US-9,799,584 Heat spreaders with integrated preforms
Embodiments of heat spreaders with integrated preforms, and related devices and methods, are disclosed herein. In some embodiments, a heat spreader may include:...
US-9,799,583 Semiconductor devices and methods of formation thereof
In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of...
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