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Patent # Description
US-9,799,582 Bump structure design for stress reduction
Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die....
US-9,799,581 Integrated fan-out structure with openings in buffer layer
A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer...
US-9,799,580 Semiconductor device package and methods of manufacture thereof
A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach...
US-9,799,579 Semiconductor substrate-on-semiconductor substrate package and method of manufacturing the same
A semiconductor assembly includes a first semiconductor substrate having a first main surface and a second main surface and a second semiconductor substrate...
US-9,799,578 Peak-based endpointing for chemical mechanical polishing
A method of polishing includes storing a predetermined location and a predetermined number as criteria for detecting an end point, polishing a substrate,...
US-9,799,577 Heat treatment system, heat treatment method, and program
A heat treatment system includes a heat treatment condition storing unit that stores a heat treatment condition with respect to a doping processing and a...
US-9,799,576 Monitoring method and manufacturing method of semiconductor device
A monitoring method that can detect a sign of disconnection of a heat generation source is provided. Further, a highly reliable semiconductor device is...
US-9,799,575 Integrated circuit containing DOEs of NCEM-enabled fill cells
Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements ("NCEM"). Such...
US-9,799,574 Gate integrated driving circuit and a restoring method thereof, a display panel and a display apparatus
The present disclosure provides a gate integrated driving circuit and a restoring method thereof, a display panel and a display apparatus. The gate integrated...
US-9,799,573 Method and apparatus for bond-pad charging protection of reference transistor test structures
A method for preparing a reference transistor test structure having a transistor with multiple terminals is provided. The method may include placing a set of...
US-9,799,572 Manufacturing method of semiconductor device
Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over a main surface of a semiconductor...
US-9,799,571 Methods for producing integrated circuits with interposers and integrated circuits produced from such methods
Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method...
US-9,799,570 Fabrication of vertical field effect transistors with uniform structural profiles
Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods...
US-9,799,569 Method of forming field effect transistors (FETs) with abrupt junctions and integrated circuit chips with the FETs
A method of forming field effect transistors (FETs) and on Integrated Circuit (IC) chips with the FETs. Channel placeholders at FET locations are undercut at...
US-9,799,568 Field effect transistor including strained germanium fins
In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region...
US-9,799,567 Method of forming source/drain contact
A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first...
US-9,799,566 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack...
US-9,799,565 Method for forming semiconductor device structure with gate
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin...
US-9,799,564 Semiconductor structure having contact holes between sidewall spacers and fabrication method there of
The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of...
US-9,799,563 Fan-out wafer level chip package structure and manufacturing method thereof
A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate...
US-9,799,562 Vias and conductive routing layers in semiconductor substrates
Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method...
US-9,799,561 Method for fabricating a semiconductor device
A method for fabricating a semiconductor device is disclosed. The method includes forming a first interlayer insulating layer including a first trench that is...
US-9,799,560 Self-aligned structure
A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask...
US-9,799,559 Methods employing sacrificial barrier layer for protection of vias during trench formation
A method includes, for example, providing an intermediate semiconductor structure comprising a metallic layer, a patternable layer disposed over the metallic...
US-9,799,558 Method for forming conductive structure in semiconductor structure
A method for manufacturing a semiconductor structure is provided. The method includes forming a first dielectric layer over a substrate and forming a...
US-9,799,557 Semiconductor device structure with metal ring on silicon-on-insulator (SOI) substrate
In accordance with some embodiments, a semiconductor device is provided. The semiconductor device structure includes a substrate, and the substrate has a device...
US-9,799,556 Land side and die side cavities to reduce package z-height
A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die...
US-9,799,555 Cobalt interconnects covered by a metal cap
Interconnects for a chip and methods of forming such interconnects. An opening is formed in a dielectric layer and a contact is formed in the opening. A metal...
US-9,799,554 Method for coating a substrate
A method for coating substrates provided with vias uses a first step in which the substrate is conditioned and a second step in which the substrate is coated...
US-9,799,553 Method for manufacturing semiconductor device with nano-gaps
A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a substrate, a first capping layer formed above the...
US-9,799,552 Low resistance metal contacts to interconnects
A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a...
US-9,799,551 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device may include forming an insulating layers on a substrate, forming a plurality of holes in an upper portion of...
US-9,799,550 Manufacturing method for forming a semiconductor structure
The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard...
US-9,799,549 Process for manufacturing a composite structure
The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a...
US-9,799,548 Susceptors for enhanced process uniformity and reduced substrate slippage
Apparatus for supporting a substrate are provided herein. In some embodiments, a substrate support includes a susceptor plate having a top surface; a recess...
US-9,799,547 Compliant bipolar micro device transfer head with silicon electrodes
A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described....
US-9,799,546 Semiconductor manufacturing apparatus and method of operating the same
In one embodiment, a semiconductor manufacturing apparatus includes an electrostatic chuck that includes a base and a first electrode provided on the base and...
US-9,799,545 Electrostatic chuck and method of manufacturing electrostatic chuck
An electrostatic chuck and a manufacturing method are disclosed in which drawbacks of using an adhesive are not existent and a freedom degree of design is high....
US-9,799,544 Robot assemblies, substrate processing apparatus, and methods for transporting substrates in electronic device...
A robot assembly allowing remote actuation of a carriage supported robot. The robot assembly includes a track, a carriage moveable along the track, and a robot...
US-9,799,543 Process box, arrangements and methods for processing coated substrates
A transportable process box for processing substrates coated on one side is described. The box has a base for the placement of a first substrate in a manner...
US-9,799,542 Substrate processing apparatus
Provided is a substrate processing apparatus, including: transportation chamber maintained in an atmospheric environment where a substrate is transported; a...
US-9,799,541 Multiple wafer single bath etcher
An etcher comprises a bath, a plurality of blades, and a tunnel. The bath includes a first electrode at a first end and a second electrode at a second end. The...
US-9,799,540 Liquid processing apparatus, liquid processing method and storage medium
A substrate holding unit of a liquid processing apparatus holds a circular substrate horizontally and rotates the substrate about a vertical axis, and a...
US-9,799,539 Method and apparatus for liquid treatment of wafer shaped articles
In an apparatus for treating a wafer-shaped article, a spin chuck is provided for holding and rotating a wafer-shaped article. A liquid dispenser comprises a...
US-9,799,538 Substrate cleaning system
A substrate cleaning system has a first processing apparatus including a first holding device for holding a substrate, and a treatment solution supply device...
US-9,799,537 Processing assembly for semiconductor workpiece and methods of processing same
A processing assembly for a semiconductor workpiece generally includes a rotor assembly capable of spinning a workpiece, a chemistry delivery assembly for...
US-9,799,536 Apparatus and method for cleaning flat objects in a vertical orientation with pulsed liquid jet
An apparatus for cleaning flat objects such as semiconductor wafers with a pulsed liquid jet emitted from a group of nozzles that may be installed on one or on...
US-9,799,535 Heat-treatment furnace
The disclosed heat-treatment furnace, used in a semiconductor-substrate heat-treatment step, is characterized by the provision of a cylindrical core, both ends...
US-9,799,534 Application of titanium-oxide as a patterning hardmask
An organic planarization layer (OPL) is formed above a functional layer located on a substrate. A titanium-oxide layer is formed above the OPL, wherein forming...
US-9,799,533 Methods of etching films comprising transition metals
Provided are methods for etching films comprising transition metals. Certain methods involve activating a substrate surface comprising at least one transition...
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