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Patent # Description
US-9,799,428 Conductor marker
A connector marker for identifying an electrical conductor includes a marker body formed of a synthetic plastic material and a pair of generally planar half...
US-9,799,427 Wire harness and method for producing wire harness
A lighter and more space-saving wire harness that has a function of retaining the shape of part of electric wires and an electromagnetic shield function. The...
US-9,799,426 Ribbed high density electrical cable
An electrical ribbon cable (110) includes an insulated conductor (114) extending along a longitudinal axis of the cable. The cable also includes a shielding...
US-9,799,425 High speed transmission cable
The present invention relates to a high speed transmission cable that includes a first conductor set, a dielectric film at least partially concentrically...
US-9,799,424 Hybrid cable, method for its manufacture and use of such a hybrid cable
An electric lead contains at least three conductors. Each of conductors has a line which is surrounded by a conductor sheath. Two of the conductors are embodied...
US-9,799,423 Cable and method of manufacturing the same
A cable is provided and includes a first conductor, a second conductor, and a PTC material layer. The PTC material layer is directly bonded to and electrically...
US-9,799,422 Insulated electrical wire and coaxial cable
An insulated electrical wire that includes a conductor and an insulating layer covering a circumferential surface of the conductor, in which the insulating...
US-9,799,421 Thick print copper pastes for aluminum nitride substrates
The invention provides an electroconductive paste comprising 50-90 wt. % of copper particle, 0.5-10 wt. % of a glass frit, 0.1-5% wt. % of adhesion promoter,...
US-9,799,420 Conductive aniline polymer, method for producing same, and method for producing conductive film
When measuring the molecular mass distribution of conductive aniline polymer of formula (1) by GPC and converting its retention time into molecular mass (M) in...
US-9,799,419 Tritium direct conversion semiconductor device for use with gallium arsenide or germanium substrates
A device for producing electricity. In one embodiment the device comprises a germanium substrate doped a first dopant type and a plurality of stacked material...
US-9,799,418 Method of treating radioactive liquid waste and radioactive liquid waste treatment apparatus
Provided is a method of treating radioactive liquid waste which reduces the amount of radioactive waste to be generated and is capable of removing a radioactive...
US-9,799,417 Method and system for the thermoelectric conversion of nuclear reactor generated heat
A method and system for the thermoelectric conversion of nuclear reactor generated heat including upon a nuclear reactor system shutdown event, ...
US-9,799,416 Methods and systems for migrating fuel assemblies in a nuclear fission reactor
Illustrative embodiments provide methods and systems for migrating fuel assemblies in a nuclear fission reactor, methods of operating a nuclear fission...
US-9,799,415 Method for controlling aluminum dissolution
A process for controlling the dissolution of a metal in an acid bath is described. The metal may comprise aluminum and the acid bath may contain a metal...
US-9,799,414 Nuclear fuel bundle containing thorium and nuclear reactor comprising same
Fuel bundles for a nuclear reactor are disclosed, and in some embodiments include a first fuel element including thorium dioxide; a second fuel element...
US-9,799,413 Multi-domain fuse management
A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains...
US-9,799,412 Memory having a plurality of memory cells and a plurality of word lines
A memory includes a plurality of replacement word lines interspersed among the plurality of word lines. The memory also includes a word line control circuit...
US-9,799,411 Memory module set having offset memory module units facilitating pin connections to main IC, and semiconductor...
A memory module set includes a main integrated circuit (IC) for transmitting and receiving an electrical signal, a first group of memory modules including at...
US-9,799,410 Method for programming antifuse-type one time programmable memory cell
A method for programming an antifuse-type OTP memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse...
US-9,799,409 Read-only memory (ROM) architecture with selective encoding
Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to...
US-9,799,408 Memory circuit with leakage compensation
A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the...
US-9,799,407 Method for operating storage device managing wear level depending on reuse period
A storage device includes a flash memory and a memory controller. The flash memory includes a plurality of memory blocks. The memory controller is configured to...
US-9,799,406 Memory system
A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of...
US-9,799,405 Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction
A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory...
US-9,799,404 Memory device, memory system and method of operating memory device
A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic...
US-9,799,403 Semiconductor memory device
A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate...
US-9,799,402 Nonvolatile memory device and program method thereof
A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile...
US-9,799,401 Incremental step pulse programming
The disclosed technology provides enables incremental step pulse programming (ISPP) operations with variable pulse step height control. In particular, a storage...
US-9,799,400 Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance
A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to...
US-9,799,399 Nonvolatile memory devices including controller for operating nonvolatile memory cell array layer in memory...
A nonvolatile memory module including a plurality of memory chips and a module controller on a printed circuit board (PCB) may be provided. Each of the...
US-9,799,398 Memory cell verification circuits, memory cell sense circuits and memory cell verification methods
Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a...
US-9,799,397 Management of data storage in memory cells using a non-integer number of bits per cell
A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally...
US-9,799,396 Semiconductor device
A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is...
US-9,799,395 Sense amplifier in low power and high performance SRAM
A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns....
US-9,799,394 Static random access memory (SRAM) with recovery circuit for a write operation
A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The...
US-9,799,393 Methods, apparatus and system for providing NMOS-only memory cells
A memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit...
US-9,799,392 Memory device comprising electrically floating body transistor
A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at...
US-9,799,391 Dram circuit, redundant refresh circuit and refresh method
A DRAM circuit includes an array having a normal word line, a first redundant word line and a second redundant word line immediately adjacent to the first...
US-9,799,390 Memory for storing the number of activations of a wordline, and memory systems including the same
A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array...
US-9,799,389 Circuit and method for imprint reduction in FRAM memories
A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B.sub.0, B.sub.1). A...
US-9,799,388 Charge sharing between memory cell plates using a conductive path
Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to...
US-9,799,387 Integrated circuits with programmable memory cells and methods for programming the same
Integrated circuits with memory cells and methods of programming the memory cells are provided. In an exemplary embodiment, a method of programming a memory...
US-9,799,386 STT MRAM midpoint reference cell allowing full write
Improved STT MRAM midpoint reference cell configurations are provided. In one aspect, a STT MRAM midpoint reference cell includes: a plurality of word lines...
US-9,799,385 Resistance change memory
According to one embodiment, a resistance change memory includes a memory cell, a reference voltage generating circuit, a first transistor and a sense...
US-9,799,384 Multi-bit MRAM cell and method for writing and reading to such MRAM cell
A multi-bit magnetic random access memory (MRAM) cell including a magnetic tunnel junction including: a first magnetic storage layer, a second magnetic storage...
US-9,799,382 Method for providing a magnetic junction on a substrate and usable in a magnetic device
A method for providing a magnetic junction usable in a magnetic device and a magnetic junction are described. A reference layer, a crystalline MgO tunneling...
US-9,799,381 Double-polarity memory read
Circuits, systems, and methods for double-polarity reading of double-polarity stored data information are described. In one embodiment, a method involves...
US-9,799,380 Managing open tabs of an application
Systems and methods for managing open tabs of an application are provided. In some aspects, a page is presented in a first tab from among multiple tabs open in...
US-9,799,379 Hold time aware register file module and method therefor
A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged...
US-9,799,378 Apparatuses and methods for performing compare operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can...
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