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Patent # Description
US-9,805,814 Memory system performing wear leveling using average erase count value and operating method thereof
A memory system may include a memory device including 0.sup.th to N-1.sup.th memory blocks, wherein N is a positive integer; and a controller having a first...
US-9,805,813 Reduction of power consumption in flash memory
Technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate...
US-9,805,812 Operating method of storage device
An operating method of a storage device which includes a nonvolatile memory is provided. The operating method includes performing a first program operation on...
US-9,805,811 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal...
US-9,805,810 Memory device with progressive row reading and related reading method
A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row...
US-9,805,809 State-dependent read compensation
Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells comprising...
US-9,805,808 Semiconductor device and method for operating the same
According to one embodiment, a semiconductor device includes a memory cell array, word lines, bit lines, a source line, and a circuit controlling a read...
US-9,805,807 Operation method operating nonvolatile memory device having plurality of memory blocks
A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A...
US-9,805,806 Non-volatile memory cell and method of operating the same
A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region,...
US-9,805,805 Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making...
A buried source semiconductor layer and p-doped semiconductor material portions are formed over a first portion of a substrate. The buried source semiconductor...
US-9,805,804 Semiconductor memory device and data erasing method
A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group...
US-9,805,803 Circuit for adjusting a select gate voltage of a non-volatile memory during erasure of memory cells based on a...
A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, an adjustment unit, and a...
US-9,805,802 Memory device, memory module, and memory system
A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions....
US-9,805,801 Memory devices and methods of their operation during a programming operation
Methods of operating a memory device during a programming operation, and memory devices so configured, including increasing a voltage applied to a selected...
US-9,805,800 Electrically programmable read only memory devices having uniform program characteristic and methods of...
An EPROM device includes bit lines branching from a supply voltage line, a first group of enablement signal lines intersecting the bit lines, unit cells...
US-9,805,799 Devices and methods of managing nonvolatile memory device having single-level cell and multi-level cell areas
A nonvolatile memory device includes a first area of single-level cells (SLCs) and a second area of multi-level cells (MLCs). The device determines whether a...
US-9,805,798 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a...
US-9,805,797 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second...
US-9,805,796 Non-volatile memory device and operating method thereof
A non-volatile memory device includes a first floating gate unit, a second floating gate unit, a selecting gate unit and a comparator. The first floating gate...
US-9,805,795 Zero leakage, high noise margin coupled giant spin hall based retention latch
A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin...
US-9,805,794 Enhanced erasing of two-terminal memory
Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in...
US-9,805,793 Filament confinement in reversible resistance-switching memory elements
A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between...
US-9,805,792 Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and...
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In...
US-9,805,791 Resistive memory structure for single or multi-bit data storage
A resistive memory structure comprises at least one resistive memory element configured to store one or more bits of data and a circuit electrically connected...
US-9,805,790 Memory cell with retention using resistive memory
Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting...
US-9,805,789 Oxide based memory
Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory...
US-9,805,788 Array power supply-based screening of static random access memory cells for bias temperature instability
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory...
US-9,805,787 Calibration circuit and memory device including the same
A memory device may include a calibration circuit configured to perform a calibration operation of generating a pull-up control code and a pull-down control...
US-9,805,786 Apparatuses and methods for a memory device with dual common data I/O lines
Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O...
US-9,805,785 Electronic device
An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a...
US-9,805,784 Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers
Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the...
US-9,805,783 Semiconductor device
A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a...
US-9,805,782 Memory device capable of determining candidate wordline for refresh and control method thereof
A memory device includes an address generation circuit, an address processing circuit and a refresh control circuit. The address generation circuit generates a...
US-9,805,781 Semiconductor memory device
A method of controlling a magnetoresistive random access memory includes receiving first signals associated with an active state through command/address pins;...
US-9,805,780 Nonvolatile memory with magnetoresistive element and transistor
A nonvolatile memory of an embodiment includes: first through fifth wirings; and a memory cell including: a first circuit including a first magnetoresistive...
US-9,805,779 Writing to multi-port memories
A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a...
US-9,805,778 Method and apparatus for timing adjustment
A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A...
US-9,805,777 Sense amplifier
Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron...
US-9,805,776 Memory device, peripheral circuit thereof and single-byte data write method thereof
A memory device, a peripheral circuit thereof and a single-byte data write method thereof are provided. The peripheral circuit includes a Y decoder, a page...
US-9,805,775 Integrated circuits with improved memory controllers
An integrated circuit may include a memory controller that interfaces with memory that operates using a memory clock signal having repeating memory clock...
US-9,805,774 Semiconductor memory device, a memory module including the same, and a memory system including the same
A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power...
US-9,805,773 Dual-range clock duty cycle corrector
Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock...
US-9,805,772 Apparatuses and methods to selectively perform logical operations
The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry...
US-9,805,771 Determining a state of a cell structure
A method is suggested for determining a state of a cell structure, wherein the cell structure includes several memory cells, the method includes: (i) detecting...
US-9,805,770 Memristor access transistor controlled non-volatile memory programming methods
A set procedure of a one transistor, one memristor memory elements may comprise determining a gate voltage for the transistor based on the desired target value....
US-9,805,769 Semiconductor device having interconnection in package and method for manufacturing the same
A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second...
US-9,805,768 Three-dimensional (3D) non-volatile semiconductor memory device for loading improvement
A three-dimensional (3D) non-volatile semiconductor memory device is disclosed. The three-dimensional (3D) non-volatile semiconductor memory device includes: a...
US-9,805,767 Perspective view entertainment system and method
In a method according to the present disclosure, a director's view version of a film is recorded. Then the film is recorded from the viewpoint of a different...
US-9,805,766 Video processing and playing method and video processing apparatus thereof
A video processing and playing method adapted to a video processing apparatus is provided. The method includes the following steps. A digital video is received...
US-9,805,765 Recording apparatus, reproducing apparatus, recording/reproducing apparatus, image pickup apparatus, recording...
A recording apparatus is disclosed. The recording apparatus includes a data input portion configured to input data, a first moving image signal recording...
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