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Patent # Description
US-9,812,566 LDMOS device having a low angle sloped oxide
A laterally diffused metal oxide semiconductor (LDMOS) device that may include an oxide region that comprises a bottom surface; a drain that is positioned...
US-9,812,565 N-channel double diffusion MOS transistor with p-type buried layer underneath n-type drift and drain layers,...
A MOS transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the...
US-9,812,564 Split-gate MOSFET
A split-gate MOSFET includes first and second epitaxial layers, first, second, and third gates, a gate oxide layer, a trench oxide layer, and a trench...
US-9,812,563 Transistor with field electrodes and improved avalanche breakdown behavior
A transistor cell includes, in a semiconductor body, a drift region of a first doping type, a source region of the first doping type, a body region of a second...
US-9,812,562 Semiconductor structure, HEMT structure and method of forming the same
A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional...
US-9,812,561 Semiconductor device manufacturing method, including substrate thinning and ion implanting
In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an...
US-9,812,560 Field effect transistor and method for manufacturing the same
Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided...
US-9,812,559 FINFET semiconductor devices and method of forming the same
Provided are a semiconductor device and a method of fabricating the same. The method comprises forming an active fin extending along a first direction; forming...
US-9,812,558 Three-dimensional transistor and methods of manufacturing thereof
A method includes providing a substrate having a mesa, forming a first opening in the mesa, the first opening being surrounded by first inner sidewalls of the...
US-9,812,557 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming an active fin extending longitudinally in a first direction along a surface of a substrate,...
US-9,812,556 Semiconductor device and method of manufacturing the semiconductor device
A method of manufacturing a semiconductor device includes forming a plurality of fin structures on a substrate, the plurality of fin structures including a...
US-9,812,555 Bottom-gate thin-body transistors for stacked wafer integrated circuits
An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having...
US-9,812,554 Method for manufacturing a semiconductor device with increased breakdown voltage
According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second...
US-9,812,553 Unipolar spacer formation for finFETs
A method for forming a spacer for a semiconductor device includes patterning gate material in a transverse orientation relative to semiconductor fins formed on...
US-9,812,552 Methods for fabricating semiconductor devices
Methods of forming a semiconductor device are provided. The methods may include forming a gate structure on a substrate, forming a first sacrificial pattern and...
US-9,812,551 Method of forming the gate electrode of field effect transistor
This description relates to a method of forming the gate electrode of a semiconductor device, the method including providing a substrate comprising a dummy gate...
US-9,812,550 Semiconductor structure with multiple transistors having various threshold voltages
A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second...
US-9,812,549 Formation method of semiconductor device structure
One or more formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate...
US-9,812,548 Power device having a polysilicon-filled trench with a tapered oxide thickness
In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected...
US-9,812,547 Semiconductor device having fin-shaped semiconductor layer
An SGT production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a...
US-9,812,546 Tungsten gates for non-planar transistors
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate...
US-9,812,545 Electronic device for data storage and a method of producing an electronic device for data storage
An electronic device for data storage and a method of producing an electronic device for data storage includes a memory storage element arranged to represent...
US-9,812,544 Semiconductor device and manufacturing method thereof
To manufacture a transistor whose threshold voltage is controlled without using a backgate electrode, a circuit for controlling the threshold voltage, and an...
US-9,812,543 Common metal contact regions having different Schottky barrier heights and methods of manufacturing same
Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include...
US-9,812,542 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating...
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
US-9,812,541 Array substrate, method for fabricating the same and display device
A method for fabricating an array substrate is disclosed, the array substrate includes a first TFT and a pixel electrode. The method includes: forming a buffer...
US-9,812,540 Enhanced switch device and manufacturing method therefor
An enhanced switch device and a manufacturing method therefor. The method comprises: providing a substrate, and forming a nitride transistor structure on the...
US-9,812,539 Semiconductor devices having buried contact structures
Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the...
US-9,812,538 Buried bus and related method
A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried...
US-9,812,537 Semiconductor device and method for manufacturing the same
A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first...
US-9,812,536 Reverse tone self-aligned contact
The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In...
US-9,812,535 Method for manufacturing a semiconductor device and power semiconductor device
A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having a first side; forming a trench in the semiconductor...
US-9,812,534 Semiconductor device and method of manufacturing the same
A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed...
US-9,812,533 Method for manufacturing semiconductor device
One object of one embodiment of the present invention is to provide a highly reliable semiconductor device including an oxide semiconductor, which has stable...
US-9,812,532 III-nitride P-channel transistor
A field effect transistor includes a III-Nitride channel layer, a III-Nitride doped cap layer on the channel layer, a source electrode in contact with the...
US-9,812,531 Light emitting device having vertical structure and package thereof
A light emitting device package can include a sub-mount having a first surface, a second surface, a bottom surface and a cavity; a first layer on the first...
US-9,812,530 High germanium content silicon germanium fins
Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that...
US-9,812,529 Semiconductor device and method for manufacturing the same
A semiconductor device of an embodiment includes a SiC layer, a gate electrode, a gate insulating layer provided between the SiC layer and the gate electrode,...
US-9,812,528 Semiconductor device
A semiconductor device according to an embodiment includes a cell region, a gate connection region, and a cell end region between the cell region and the gate...
US-9,812,527 Growth of semiconductors on hetero-substrates using graphene as an interfacial layer
Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any...
US-9,812,526 Three-dimensional semiconductor devices
A three-dimensional (3D) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the...
US-9,812,525 Universal methodology to synthesize diverse two-dimensional heterostructures
A two-dimensional heterostructure is synthesized by producing a patterned first two-dimensional material on a growth substrate. The first two-dimensional...
US-9,812,524 Nanowire transistor devices and forming techniques
Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within...
US-9,812,523 Capacitance structure
A capacitance structure includes a first input terminal configured to input a first input signal, a first output terminal configured to output the first output...
US-9,812,522 Metal-insulator-metal capacitor fabrication with unitary sputtering process
A metal-insulator-metal capacitor includes a bottom electrode comprising a nitride of a metal, an insulator disposed on the bottom electrode and comprising an...
US-9,812,521 Embedded passive chip device and method of making the same
An embedded passive chip device includes a chip body and a functional layered structure. The chip body has a circuit-forming surface that is formed with a...
US-9,812,520 Display device
A display device includes, on a substrate, light emitting elements each formed by sequentially stacking a first electrode layer, an organic layer including a...
US-9,812,518 Thin film transistor array substrate and organic light-emitting display apparatus including the same
Provided is a thin film transistor array substrate. The thin film transistor array substrate includes a first sub-pixel region and a second sub-pixel region; a...
US-9,812,517 Method for manufacturing display device and method for manufacturing electronic device
A method for manufacturing a display device, which does not easily damage an electrode, is provided. In the first step, a terminal electrode, a wiring, and a...
US-9,812,516 Display panel
A display panel including: a substrate; and a plurality of line banks arranged along a specific direction on the substrate, wherein the line banks are each...
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