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Patent # Description
US-9,812,464 Three-dimensional semiconductor device
A three-dimensional semiconductor device may include a lower electrode structure having a plurality of lower electrodes vertically stacked on a substrate and an...
US-9,812,463 Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof
A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop...
US-9,812,462 Memory hole size variation in a 3D stacked memory
Techniques are provided for fabricating a memory device in which the memory cells have a uniform program and erase speed. In one aspect, a memory device is...
US-9,812,461 Honeycomb cell structure three-dimensional non-volatile memory device
A monolithic three-dimensional memory device includes a plurality of memory stack structures arranged in a hexagonal lattice and located over a substrate. The...
US-9,812,460 NVM memory HKMG integration technology
The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high...
US-9,812,459 Embedded SRAM and methods of forming the same
A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor...
US-9,812,458 Memory device and method for manufacturing the same
A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as...
US-9,812,457 Ultra high density integrated composite capacitor
Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS)...
US-9,812,456 Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory...
US-9,812,455 Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias
A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions...
US-9,812,454 Methods and systems for reducing electrical disturb effects between thyristor memory cells using buried metal...
Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between...
US-9,812,453 Self-aligned sacrificial epitaxial capping for trench silicide
A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include forming a Si fin in...
US-9,812,452 Method to form silicide and contact at embedded epitaxial facet
An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an...
US-9,812,451 Field effect transistor contact with reduced contact resistance
The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate...
US-9,812,450 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring...
US-9,812,449 Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance
A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet...
US-9,812,448 Semiconductor devices and methods for fabricating the same
Provided are a semiconductor device configured to block a physical diffusion path by forming an oxide layer between barrier layers to prevent impurities from...
US-9,812,447 Bipolar junction transistors with extrinsic device regions free of trench isolation
Device structures and fabrication methods for a device structure. One or more trench isolation regions are formed in a substrate to surround a device region. A...
US-9,812,446 Electronic apparatus with pocket of low permittivity material to reduce electromagnetic interference
An electronics apparatus including a first substrate having a first surface and a second surface, a first switch connected to a second switch and soldered in...
US-9,812,445 Bipolar junction transistor device having base epitaxy region on etched opening in DARC layer
A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active...
US-9,812,444 Fin-type resistor
A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a...
US-9,812,443 Forming vertical transistors and metal-insulator-metal capacitors on the same chip
A device with a vertical transistor and a metal-insulator-metal (MIM) capacitor on a same substrate includes a vertical transistor including a bottom...
US-9,812,442 Integrated semiconductor device and manufacturing method therefor
An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of...
US-9,812,441 Semiconductor integrated circuit device
In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the...
US-9,812,440 Biased ESD circuit
This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with...
US-9,812,439 Bi-directional ESD protection circuit
An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated...
US-9,812,438 Avalanche diode having an enhanced defect concentration level and method of making the same
The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the...
US-9,812,437 Semiconductor integrated circuit device, and electronic appliance using the same
Provided is a semiconductor integrated circuit device including: an output buffer circuit having a P channel transistor connected between a first power supply...
US-9,812,436 SCRs with checker board layouts
An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of...
US-9,812,435 Semiconductor device
An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second...
US-9,812,434 Hollow metal pillar packaging scheme
An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The...
US-9,812,433 Batch process fabrication of package-on-package microelectronic assemblies
A microelectronic assembly can be made by joining first and second subassemblies by electrically conductive masses to connect electrically conductive elements...
US-9,812,432 LED chip package
An LED chip package includes a substrate having a metal terminal (gold finger structure). A LED chip set is composed of a plurality of LED chips formed in one...
US-9,812,431 Power semiconductor module
A power semiconductor module is equipped with: a metal base; semiconductor chips electrically connected with and fixed to the metal base; and an insulating...
US-9,812,430 Package on-package method
A method comprises forming a trench over a top surface of a metal structure of a bottom package, dispersing an epoxy flux material in the trench, mounting a top...
US-9,812,429 Interconnect structures for assembly of multi-layer semiconductor devices
A multi-layer semiconductor device includes a first semiconductor structure having first and second opposing surfaces, the second surface of the first...
US-9,812,428 Vertically integrated wafers with thermal dissipation
Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some...
US-9,812,427 Package on-package (PoP) structure including stud bulbs
Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure...
US-9,812,426 Integrated fan-out package, semiconductor device, and method of fabricating the same
A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one...
US-9,812,425 Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same
Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an...
US-9,812,424 Process of forming an electronic device including a ball bond
A process of forming an electronic device includes providing a wire comprising a first ball at an end thereof, operating on the first ball to modify a surface...
US-9,812,423 Semiconductor device having wire formed with loop portion and method for producing the semiconductor device
A semiconductor device includes: a connection terminal; a semiconductor chip having an electrode pad on one surface; a wire that connects the connection...
US-9,812,421 Bonding wire for semiconductor devices
Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol %...
US-9,812,420 Die packaging with fully or partially fused dielectric leads
A die interconnect system having a first die with a plurality of connection pads, and a ribbon lead extending from the first die, the ribbon lead having a...
US-9,812,418 Electronic apparatus and method for fabricating the same
An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and...
US-9,812,417 Semiconductor device and semiconductor device manufacturing method
The present disclosure provides a semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions...
US-9,812,416 Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer...
US-9,812,415 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a...
US-9,812,414 Chip package and a manufacturing method thereof
A chip package includes a first substrate; a first insulation layer disposed over the first substrate; a conductive structure disposed within the first...
US-9,812,413 Chip module and method for forming the same
A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region...
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