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Patent # Description
US-9,812,412 Chip part having passive elements on a common substrate
A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which...
US-9,812,411 Semiconductor device, inverter circuit, and drive device
A semiconductor device of an embodiment includes a first electrode, a second electrode facing the first electrode, an alternating-current electrode, a first...
US-9,812,410 Lid structure for a semiconductor device package and method for forming the same
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure...
US-9,812,409 Seal ring structure with a metal pad
A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first...
US-9,812,408 Semiconductor device with electrostatic discharge protection device near the edge of the chip
A semiconductor device has a supply pad to which a supply voltage is fed, a supply conductor that is electrically connected to the supply pad, an input/output...
US-9,812,407 Self-destructing electronic device
A self destructing device includes: at least one active electronic region and at least one thermal destruction trigger; at least one chamber enclosed by the...
US-9,812,406 Microelectronic assemblies with cavities, and methods of fabrication
Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the...
US-9,812,405 Semiconductor package and manufacturing method of the same
The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a...
US-9,812,404 Electrical connection around a crackstop structure
The disclosure generally relates to semiconductor structures and, more particularly, to electrical connections used with crackstop structures and methods of...
US-9,812,403 Reducing wafer warpage during wafer processing
A manufacturing method of a semiconductor device that can reduce warpage during wafer processing. The method includes forming a first guard ring around a first...
US-9,812,402 Wire bond wires for interference shielding
Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper...
US-9,812,401 Techniques for observing an entire communication bus in operation
A routing apparatus includes a PCB having first and second arrays of contact pads, an interposer having third, fourth and fifth arrays of contact pads, the...
US-9,812,400 Contact line having insulating spacer therein and method of forming same
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a...
US-9,812,399 Prevention of premature breakdown of interline porous dielectrics in an integrated circuit
A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of...
US-9,812,398 Semiconductor memory device having memory cells provided in a height direction
According to an embodiment, a semiconductor memory device comprises: a memory string comprising a plurality of memory cells connected in series therein; and a...
US-9,812,397 Method of forming hybrid diffusion barrier layer and semiconductor device thereof
In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At...
US-9,812,396 Interconnect structure for semiconductor devices with multiple power rails and redundancy
A method includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a first metallization...
US-9,812,395 Methods of forming an interconnect structure using a self-ending anodic oxidation
A method of forming low-k interconnect structure is disclosed, which comprises: providing at least one protruding structure on a substrate traversing between a...
US-9,812,394 Faceted structure formed by self-limiting etch
An eFuse device on a substrate is formed on a substrate used for an integrated circuit. A semiconductor structure is created from a semiconductor layer...
US-9,812,393 Programmable via devices with metal/semiconductor via links and fabrication methods thereof
Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second...
US-9,812,392 Inductor system and method
A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors....
US-9,812,391 Advanced metallization for damage repair
An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the...
US-9,812,390 Semiconductor devices including conductive features with capping layers and methods of forming the same
Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an...
US-9,812,389 Isolation device
An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a...
US-9,812,388 Semiconductor device and manufacturing method thereof
A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the...
US-9,812,387 Semiconductor substrate, semiconductor module and method for manufacturing the same
A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second...
US-9,812,386 Encapsulated semiconductor package
An encapsulated semiconductor package. As non-limiting examples, various aspects of the present disclosure provide an integrated circuit package comprising a...
US-9,812,385 Electronic component package including electronic component, metal member, and sealing resin
An electronic component package according to one aspect of the present disclosure includes a metal pattern layer having a first principal surface and a second...
US-9,812,384 Semiconductor device having compliant and crack-arresting interconnect structure
A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first...
US-9,812,383 Power converter package using driver IC
A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control...
US-9,812,382 Semiconductor device with lead terminals having portions thereof extending obliquely
A semiconductor device includes a semiconductor chip and a plurality of leads. The leads include a first lead including a supporting portion for mounting the...
US-9,812,381 Integrated fan-out package and method of fabricating the same
An integrated fan-out package is described. The integrated fan-out package comprises a first die and a second die arranged adjacent to each other. A molding...
US-9,812,380 Bumps bonds formed as metal line interconnects in a semiconductor device
A semiconductor power chip has a semiconductor power device formed on a semiconductor die; wherein the semiconductor power device comprises an array of...
US-9,812,379 Semiconductor package and manufacturing method
A semiconductor package includes a die comprising at least a via and a least a hot via; a ground lead, formed directly under a back side of the die, contacting...
US-9,812,378 Packaging for high power integrated circuits and infrared emitter arrays
A product and method for packaging high power integrated circuits or infrared emitter arrays for operation through a wide range of temperatures, including...
US-9,812,377 Semiconductor module and inverter device
In a semiconductor module of the invention, a heat sink has a convex portion in which a convex plane has an area smaller than a joint area to the joint layer, a...
US-9,812,376 Electrically conductive element, power semiconductor device having an electrically conductive element and...
An electrically conductive element includes an electrically conductive material and a plurality of inclusions of a phase change material. The phase change...
US-9,812,375 Composite substrate with alternating pattern of diamond and metal or metal alloy
A composite substrate includes a submount substrate of an alternating pattern of electrically insulative portions, pieces, layers or segments and electrically...
US-9,812,374 Thermal management device with textured surface for extended cooling limit
Methods and apparatus are described for heat management in an integrated circuit (IC) package using a device with a textured surface having multiple grooves in...
US-9,812,373 Semiconductor package with top side cooling heat sink thermal pathway
An electronic module includes a semiconductor package including a semiconductor chip and an electrically insulating encapsulation body encapsulating the...
US-9,812,372 Electrostatic chuck assembly, semiconductor manufacturing apparatus having the same, and method of measuring...
An electrostatic chuck assembly includes a reference temperature sensor, a measurement zone temperature sensor, and a measurement zone temperature calculator....
US-9,812,371 Methods for reducing metal contamination on a surface of a sapphire substrate by plasma treatment
The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of...
US-9,812,370 III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology
In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the...
US-9,812,369 BiMOS device with a fully self-aligned emitter-silicon and method for manufacturing the same
A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation...
US-9,812,368 Method to prevent lateral epitaxial growth in semiconductor devices
The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure. Each of...
US-9,812,367 Method for fabricating semiconductor device including replacement process of forming at least one metal gate...
A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced...
US-9,812,366 Method of tuning work function for a semiconductor device
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes forming pre-tuned-work-function (preTWF) layer over a...
US-9,812,365 Methods of cutting gate structures on transistor devices
One illustrative method disclosed includes, among other things, forming a plurality of gates above a substrate, each of the gates comprising a gate structure...
US-9,812,364 Method of fabricating semiconductor device with an overlay mask pattern
The disclosure relates to methods of fabricating semiconductor devices. A method of fabricating a semiconductor device is provided as follows. A target layer is...
US-9,812,363 FinFET device and method of forming same
A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin....
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