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Patent # Description
US-9,818,892 Solar cell and method of fabricating the same
A solar cell includes a back electrode layer provided on a support substrate and including a first through hole, a light absorbing layer provided on the first...
US-9,818,891 Solar cell module and method for manufacturing the same
A solar cell module and a method for manufacturing the same are disclosed. The method for manufacturing the solar cell module includes applying a low melting...
US-9,818,890 Solar cell contacts with nickel intermetallic compositions
Paste compositions, methods of making a paste composition, and methods of making a solar cell contact are disclosed. The paste composition can contain a nickel...
US-9,818,889 Composition for solar cell electrodes and electrode fabricated using the same
A composition for solar cell electrodes, a solar cell electrode prepared from the composition, a solar cell, and a method of manufacturing the same, the...
US-9,818,888 Article with buffer layer and method of making the same
A method of forming a coating layer on a glass substrate in a glass manufacturing process includes: providing a first coating precursor material for a selected...
US-9,818,887 Back-illuminated sensor with boron layer
An inspection system including an optical system (optics) to direct light from an illumination source to a sample, and to direct light reflected/scattered from...
US-9,818,886 Semiconductor device
The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky...
US-9,818,885 Deposited material and method of formation
A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition...
US-9,818,884 Strain compensation in transistors
An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the...
US-9,818,883 Metal oxide thin film transistor and preparation method thereof, as well as array substrate
A metal oxide thin film transistor and a preparation method thereof, as well as an array substrate, wherein the metal oxide thin film transistor comprises a...
US-9,818,882 Semiconductor device
A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for...
US-9,818,881 Semiconductor device and manufacturing method of semiconductor device
A semiconductor device includes an oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide...
US-9,818,880 Semiconductor device and display device including the semiconductor device
To reduce parasitic capacitance in a semiconductor device having a transistor including an oxide semiconductor. The transistor includes a first gate electrode,...
US-9,818,879 Integrated circuit devices
An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction...
US-9,818,878 FETs and methods for forming the same
FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and...
US-9,818,877 Embedded source/drain structure for tall finFET and method of formation
A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench...
US-9,818,875 Approach to minimization of strain loss in strained fin field effect transistors
A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a...
US-9,818,874 Method for fabricating semiconductor structures including fin structures with different strain states, and...
Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor...
US-9,818,873 Forming stressed epitaxial layers between gates separated by different pitches
Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a...
US-9,818,872 Multi-gate device and method of fabrication thereof
A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel...
US-9,818,871 Defense layer against semiconductor device thinning
In one embodiment, a semiconductor device comprises one or more defense layers, the one or more defense layers each characterized by at least two lattice...
US-9,818,870 Transistor structure with variable clad/core dimension for stress and bandgap
An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first...
US-9,818,869 Ferroelectric device and method of its manufacture
A ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as...
US-9,818,868 Metal oxide semiconductor and method of making
A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the...
US-9,818,867 Simple and cost-free MTP structure
Non-volatile (NV) Multi-time programmable (MTP) memory cells are presented. The memory cell includes a substrate and first and second wells in the substrate....
US-9,818,866 Junction FET semiconductor device with dummy mask structures for improved dimension control and method for...
A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate...
US-9,818,865 Semiconductor device including a pipe channel layer having a protruding portion
Disclosed is a semiconductor device, including: a first pipe gate; a second pipe gate on the first pipe gate; a stacked structure on the second pipe gate; a...
US-9,818,864 Vertical nanowire transistor with axially engineered semiconductor and gate metallization
Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In...
US-9,818,863 Integrated breakdown protection
A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area,...
US-9,818,862 Semiconductor device with floating field plates
A semiconductor device with a current terminal region located in a device active area of a substrate of the device. A guard region is located in a termination...
US-9,818,861 Semiconductor device and method for forming the same
A semiconductor device including a substrate having a drain region therein is provided. A gate-electrode layer is disposed on the drain region. A first...
US-9,818,860 Silicon carbide semiconductor device and method for producing the same
An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region....
US-9,818,859 Quasi-vertical power MOSFET and methods of forming the same
A MOSFET includes a semiconductor substrate having a top surface, a body region of a first conductivity type in the semiconductor substrate, and a double...
US-9,818,858 Multi-layer active layer having a partial recess
A transistor with a multi-layer active layer having at least one partial recess is provided. The transistor includes a channel layer arranged over a substrate....
US-9,818,857 Fault tolerant design for large area nitride semiconductor devices
A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor...
US-9,818,856 Semiconductor device with high electron mobility transistor
A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron...
US-9,818,855 Semiconductor device
A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a source electrode provided on the first nitride semiconductor...
US-9,818,854 Electronic device including a bidirectional HEMT
An electronic device can include a bidirectional HEMT. In an aspect, the electronic device can include a pair of switch gate and blocking gate electrodes,...
US-9,818,853 Semiconductor device and manufacturing method thereof
The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer...
US-9,818,852 Semiconductor device and semiconductor device manufacturing method
In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an...
US-9,818,851 Semiconductor device and manufacturing method thereof
An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a first trench gate electrode and second and third...
US-9,818,850 Manufacturing method of the semiconductor device
The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide...
US-9,818,849 Manufacturing method of semiconductor device with conductive film in opening through multiple insulating films
A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a...
US-9,818,848 Three-dimensional ferroelectric FET-based structures
Exemplary embodiments of the present disclosure are directed to three-dimensional (3D) Ferroelectric-gated FET (FeFET) structures that can be used to implement...
US-9,818,847 Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate...
A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen....
US-9,818,846 Selectively deposited spacer film for metal gate sidewall protection
A method of fabricating a fin field-effect transistor (FinFET) device is provided. The method includes forming a carbon-based layer on a plurality of gate...
US-9,818,845 MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device
A mask used to form an n.sup.+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a...
US-9,818,844 High-voltage junctionless device with drift region and the method for making the same
The present invention discloses a method of forming a high voltage junctionless device with drift region. The drift region formed between the semiconductor...
US-9,818,843 Transistor having dual work function buried gate electrode and method for fabricating the same
A transistor having a source region and a drain region which are separately formed in a substrate, a trench which is defined in the substrate between the source...
US-9,818,842 Dynamic threshold MOS and methods of forming the same
A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor...
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