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Patent # Description
US-9,818,740 Method of improving bipolar device signal to noise performance by reducing the effect of oxide interface...
An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base...
US-9,818,739 Array substrate and manufacturing method thereof, and a display device
An array substrate is provided. The array substrate includes a substrate body, a gate electrode layer, a first insulating layer, a source-drain electrode layer,...
US-9,818,738 Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells with...
An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain...
US-9,818,737 Semiconductor device and method of manufacturing the same
A semiconductor device is provided. The semiconductor device may include stacks including conductive layers and insulating layers. The conductive layers and...
US-9,818,736 Method for producing semiconductor package
A method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on...
US-9,818,735 Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device includes providing a first semiconductor chip comprising a first metallic structure, a first surface and a...
US-9,818,734 Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating...
US-9,818,733 Power converters having capacitive energy transfer elements and arrangements of energy storage elements for...
A power converter includes a PCB and a semiconductor die coupled to the PCB. The semiconductor die includes first through fourth switching devices. The power...
US-9,818,732 Chip-on-film package and device assembly including the same
Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a...
US-9,818,731 Light emitting device
The color purities of blue-green light and yellow or yellow-green light are enhanced. A light emitting device (100) configured to emit at least blue-green light...
US-9,818,730 Semiconductor arrangement, method for producing a number of chip assemblies, method for producing a...
A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode...
US-9,818,729 Package-on-package structure and method
A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor...
US-9,818,728 Interconnect structure with redundant electrical connectors and associated systems and methods
Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die...
US-9,818,727 Semiconductor package assembly with passive device
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on...
US-9,818,726 Chip stack cooling structure
An apparatus comprises a first die, a thermal cooler formed over at least a portion of the first die, a second die formed over at least a portion of the thermal...
US-9,818,725 Inorganic-light-emitter display with integrated black matrix
An inorganic-light-emitter display includes a display substrate and a plurality of spatially separated inorganic light emitters distributed on the display...
US-9,818,724 Interposer-chip-arrangement for dense packaging of chips
The interposer-chip-arrangement comprises an interposer (1), metal layers arranged above a main surface (10), a further metal layer arranged above a further...
US-9,818,723 Multi-chip package with interconnects extending through logic chip
A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having...
US-9,818,722 Package structure and method for manufacturing thereof
A package structure includes a package, at least one first molding material, and at least one second semiconductor device. The package includes at least one...
US-9,818,721 Semiconductor device and manufacturing method thereof
An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic...
US-9,818,720 Structure and formation method for chip package
Structures and formation methods of a chip package are provided. The chip package includes a first chip structure and a second chip structure. Heights of the...
US-9,818,719 Bumpless build-up layer package design with an interposer
The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL)...
US-9,818,718 Conductive paste and die bonding method
Provided are: a conductive paste in which sinterability of silver particles the conductive paste can be easily controlled by using silver particles having...
US-9,818,717 Enhanced cleaning for water-soluble flux soldering
An approach to provide an electronic assembly process that includes receiving at least one electronic assembly after a solder reflow process using a...
US-9,818,716 Power module
A power module is fabricated, employing a clad metal that is formed by pressure-laminating aluminum and copper, in such a manner that the aluminum layer of the...
US-9,818,715 Semiconductor integrated circuit device
A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a...
US-9,818,714 Method of manufacturing substrate for chip packages and method of manufacturing chip package
Provided are a method of manufacturing a substrate for chip packages and a method of manufacturing a chip package, the method of manufacturing the substrate...
US-9,818,713 Structures and methods for low temperature bonding using nanoparticles
A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive...
US-9,818,712 Package with low stress region for an electronic component
A device package includes a substrate having an active surface. Electrical connection bumps are deposited on the active surface and are arranged in an array...
US-9,818,711 Post-passivation interconnect structure and methods thereof
The semiconductor device includes a die that contains a substrate and a bond pad. A connective layer is disposed over the die. The connective layer includes a...
US-9,818,710 Anchored interconnect
An embodiment includes a semiconductor structure comprising: a backend portion including a plurality of metal layers between bottom and top metal layers; the...
US-9,818,709 Semiconductor device and manufacturing method thereof
A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting...
US-9,818,708 Semiconductor device with thin redistribution layers
A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically...
US-9,818,707 Stacked memory chip having reduced input-output load, memory module and memory system including the same
A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a...
US-9,818,706 Moisture-resistant electronic component, notably microwave, and method for packaging such a component
A component comprises at least one support on which is fixed at least one electronic circuit, for example a circuit of MMIC type, one or more layers of organic...
US-9,818,705 Semiconductor device
A semiconductor device includes at least one semiconductor element having a first terminal side and a second terminal side connected by an outer periphery...
US-9,818,704 Stress tuning for reducing wafer warpage
A method includes forming a low-k dielectric layer over a substrate of a wafer, forming a first dielectric layer over the low-k dielectric layer, forming a...
US-9,818,703 Printed circuit board
A printed circuit board includes chip regions on which semiconductor chips are mounted, and a scribe region surrounding each of the chip regions. The scribe...
US-9,818,702 Wiring substrate and semiconductor device
A wiring substrate includes a first reinforcement pattern stacked on a lower surface of a first insulation layer at a peripheral region located at an outer side...
US-9,818,701 Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device
A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers,...
US-9,818,700 Stress relief structures in package assemblies
A semiconductor package structure includes a substrate; and a die region having a plurality of dies disposed on the substrate. A first die of the plurality of...
US-9,818,699 Semiconductor packages and methods of fabricating the same
Provided is a method of fabricating a semiconductor package. The method includes providing a substrate including a plurality of semiconductor chips; forming a...
US-9,818,698 EMI package and method for making same
An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable...
US-9,818,697 Semiconductor package manufacturing method
The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an...
US-9,818,696 Semiconductor device
A semiconductor device includes: a trench; a first electrode is formed in the trench; a first impurity region, which has a first conductivity type and is formed...
US-9,818,695 Material and process for copper barrier layer
A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material...
US-9,818,694 Active atomic reservoir for enhancing electromigration reliability in integrated circuits
An integrated circuit (IC) comprises a first conductor in one layer of the IC, a second conductor in another layer of the IC, and a first metal plug connecting...
US-9,818,693 Through-memory-level via structures for a three-dimensional memory device
A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating...
US-9,818,692 GaN semiconductor device structure and method of fabrication by substrate replacement
Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched...
US-9,818,691 Semiconductor device having a fuse element
A corrosion resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous...
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