Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,818,690 Self-aligned interconnection structure and method
The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are...
US-9,818,689 Metal-insulator-metal capacitor and methods of fabrication
A method of forming a semiconductor structure, comprising forming a dual damascene structure having a capacitor trench and an interconnect trench, forming a...
US-9,818,688 Dielectric region in a bulk silicon substrate providing a high-Q passive resonator
Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive...
US-9,818,687 Semiconductor module and method of manufacturing semiconductor module
A semiconductor module includes an insulated circuit board that includes an insulating substrate, a first conductive plate arranged on a first principal surface...
US-9,818,686 Semiconductor modules and methods of forming the same
Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second...
US-9,818,685 Semiconductor device with redistribution layers on partial encapsulation and non-photosensitive passivation layers
A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include a semiconductor die having a first surface, a second...
US-9,818,684 Electronic device with a plurality of redistribution structures having different respective sizes
A semiconductor device with enhanced interposer quality, and method of manufacturing thereof. For example and without limitation, various aspects of the present...
US-9,818,683 Electronic package and method of fabricating the same
A met of fabricating an electronic package is provided, including: providing a carrier body haying a first surface formed with a plurality of recessed portions,...
US-9,818,682 Laminate substrates having radial cut metallic planes
A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a...
US-9,818,681 Wiring substrate
A wiring substrate includes a first substrate and an electronic component mounted on an upper surface of the first substrate. A first pad is formed on an...
US-9,818,680 Scalable semiconductor interposer integration
Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with...
US-9,818,679 Semiconductor device
This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a...
US-9,818,678 Semiconductor device
To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode...
US-9,818,677 Semiconductor component having group III nitride semiconductor device mounted on substrate and interconnected...
In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads...
US-9,818,676 Singulation method for semiconductor package with plating on side of connectors
A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein...
US-9,818,675 Semiconductor device including conductive clip with flexible leads and related methods
An integrated circuit (IC) device may include a leadframe and an IC die having a first surface coupled to the lead frame and a second surface opposite the first...
US-9,818,673 Cooler
A cooler includes a cooling pipe having a cooling surface in contact with a heat-exchanged component, and a refrigerant passage. A pair of outer passages are...
US-9,818,672 Flow diversion devices
Embodiments of flow diversion devices (FDDs) are disclosed herein. An FDD may include a body formed of a body material and a plurality of thermally deformable...
US-9,818,671 Liquid-cooled heat sink for electronic devices
A heat sink includes a heat absorption module, a liquid transport module and a heat exchange module. The transport module includes one inlet and outlet tubes,...
US-9,818,670 Cooling device installation using a retainer assembly
A system includes a retainer assembly to align each of a group of cooling devices with a corresponding electrical component of a group of electrical components...
US-9,818,669 Printed circuit board assembly including conductive heat transfer
A printed circuit board assembly (PCBA) may include a printed circuit board (PCB), a socket mechanically and electrically coupled to the PCB, and an integrated...
US-9,818,668 Thermal vias disposed in a substrate without a liner layer
A method relating generally to a substrate is disclosed. In such a method, the substrate has formed therein a plurality of vias. A liner layer is located on the...
US-9,818,667 Compute intensive module packaging
A package for a multi-chip module includes a top cold plate and a bottom plate whose perimeters are in thermal communication so the plates together completely...
US-9,818,666 Interconnect arrangement with stress-reducing structure and method of fabricating the same
A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a...
US-9,818,665 Method of packaging a semiconductor chip using a 3D printing process and semiconductor package having angled...
In one aspect, a method of packaging a semiconductor module includes providing a semiconductor module having a first surface, a second surface opposite the...
US-9,818,664 Electronic device comprising an encapsulating block locally of smaller thickness
An electronic device includes a carrier substrate with at least one electronic-circuit chip mounted on a front face of the carrier substrate. An encapsulation...
US-9,818,663 Silicone composition with protection against pollutants
Addition-curable encapsulants for electrical and electronic components contain amorphous glass particles doped with silver, and are efficient scavengers of...
US-9,818,662 Silicon package having electrical functionality by embedded passive components
A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a...
US-9,818,661 Semiconductor unit and test method
A semiconductor unit includes: a substrate made of a semiconductor; and a device group formed on the substrate and configured of a plurality of first...
US-9,818,660 Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with...
An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain...
US-9,818,659 Multi-die package comprising unit specific alignment and unit specific routing
A method of making a semiconductor device can include forming an embedded die panel by encapsulating a first semiconductor die and a second semiconductor die...
US-9,818,658 Semiconductor wafer processing methods and apparatus
A semiconductor wafer processing method comprising controlling the temperature of a semiconductor wafer to be within a predetermined processing temperature...
US-9,818,657 Dry etching method and method of manufacturing semiconductor device
A first etching rate of the first conductive film is calculated by acquiring correlation between an opening ratio of an etching mask and an etching rate of an...
US-9,818,656 Devices and methods for testing integrated circuit devices
A method of testing includes attaching a first and second die to first and second die sites of a lead frame and forming a plurality of wire bonds coupling a...
US-9,818,655 Method and structure for flip-chip package reliability monitoring using capacitive sensors groups
Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time...
US-9,818,654 Substrate processing apparatus and substrate processing method
An apparatus includes: measurement flow passage portions as part of a respective plurality of supply paths of fluids to be supplied to a substrate, the...
US-9,818,653 Semiconductor TSV device package to which other semiconductor device package can be later attached
A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (TSV)...
US-9,818,652 Commonly-bodied field-effect transistors
Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material...
US-9,818,651 Methods, apparatus and system for a passthrough-based architecture
At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate...
US-9,818,650 Extra gate device for nanosheet
A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is...
US-9,818,649 Method and structure for FinFET isolation
A semiconductor device includes a substrate having first and second fins extending lengthwise generally along a same line; a first gate stack over the substrate...
US-9,818,648 Method for forming Fin field effect transistor (FinFET) device structure
Methods for forming the fin field effect transistor (FinFET) device structure are provided. The method includes forming first fin structures and second fin...
US-9,818,647 Germanium dual-fin field effect transistor
In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain...
US-9,818,646 Process for fabricating an integrated circuit comprising at least one coplanar waveguide
An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the...
US-9,818,645 Through electrode, manufacturing method thereof, and semiconductor device and manufacturing method thereof
Embodiments provided are a through electrode that can be manufactured by a method not including the step of removing a side-wall insulating film formed at the...
US-9,818,644 Interconnect structure and manufacturing method thereof
The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature...
US-9,818,643 Semiconductor interconnect structure and manufacturing method thereof
The present disclosure provides an interconnect structure, including a low k dielectric layer with an air gap region and a non-air gap region. A first...
US-9,818,642 Method of forming inter-level dielectric structures on semiconductor devices
A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a...
US-9,818,641 Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines
A method includes providing a structure having a first, second and third hardmask layer and a mandrel layer disposed respectively over a dielectric stack. An...
US-9,818,640 Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines
A method includes providing a structure having a first hardmask layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.