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Patent # Description
US-9,818,639 Semiconductor device and manufacturing method thereof
The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including...
US-9,818,638 Manufacturing method of semiconductor device
A method of forming a semiconductor device includes forming a low-k dielectric layer over a substrate and forming a first dielectric layer on the low-k...
US-9,818,637 Device layer transfer with a preserved handle wafer section
Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and...
US-9,818,636 Ephemeral bonding
Compositions containing an adhesive material and a release additive are suitable for temporarily bonding two surfaces, such as a wafer active side and a...
US-9,818,635 Carrier structure, packaging substrate, electronic package and fabrication method thereof
An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed...
US-9,818,634 Storage rack
A storage rack including a plurality of storage sections further includes a plurality of columns with one column provided at each end along the right and left...
US-9,818,633 Equipment front end module for transferring wafers and method of transferring wafers
An EFEM useful for transferring wafers to and from wafer processing modules comprises an enclosure having a controlled environment therein bounded by a front...
US-9,818,632 Tray for semiconductor devices
A tray for semiconductor devices includes a base with a positioning unit. The positioning unit includes a plurality of tiered projections which jointly define...
US-9,818,631 Semiconductor device handler throughput optimization
A method and system are provided for optimizing operational throughput for a semiconductor device handler having multiple stages. The method includes receiving...
US-9,818,630 Substrate processing apparatus
A substrate processing apparatus includes a first reaction chamber including: a first heating unit, a first processing space, and a first transfer space...
US-9,818,629 Substrate processing apparatus and non-transitory computer-readable recording medium
Provided is a substrate processing apparatus capable of efficiently resuming processing of unprocessed substrates after an error occurs during processing of...
US-9,818,628 Curing apparatus and method using the same
A UV curing apparatus includes a processing chamber, a UV light source disposed above the processing chamber, a window disposed between the processing chamber...
US-9,818,627 Manufacturing method of semiconductor device and semiconductor manufacturing apparatus
A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for...
US-9,818,626 Substrate processing apparatus and substrate processing method
When a substrate W is processed, a ring-shaped protective wall is located above the substrate held by the substrate holding unit and extends in a ...
US-9,818,625 Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,818,624 Methods and apparatus for correcting substrate deformity
Embodiments of methods and apparatus for correcting substrate deformity are provided herein. In some embodiments, a substrate flattening system includes: a...
US-9,818,623 Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit
A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure...
US-9,818,622 Uniform back side exposure of through-silicon vias
Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate...
US-9,818,621 Cyclic oxide spacer etch process
Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may...
US-9,818,620 Manufacturing method of semiconductor device
In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed...
US-9,818,619 Carrier head
Provided is a carrier head. The carrier head includes: a body having a ring shape, wherein a first locking part is formed on an external surface of the body; a...
US-9,818,618 Multi-layer polishing pad for CMP
The invention is directed to a multi-layer polishing pad for chemical-mechanical polishing comprising a top layer, a middle layer and a bottom layer, wherein...
US-9,818,617 Method of electroless plating using a solution with at least two borane containing reducing agents
A solution for providing electroless deposition of a metal layer on a substrate is provided. A solvent is provided. A metal precursor is provided to the...
US-9,818,616 Controlling threshold voltage in nanosheet transistors
Embodiments are directed to a method of forming a semiconductor device and resulting structures for controlling a threshold voltage on a nanosheet-based...
US-9,818,615 Systems and methods for bidirectional device fabrication
Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a ...
US-9,818,614 Apparatus for molecular adhesion bonding with compensation for radial misalignment
A method for bonding a first wafer onto a second wafer by molecular adhesion where the wafers have an initial radial misalignment between them. The method...
US-9,818,613 Self-aligned double spacer patterning process
A method includes forming a mask layer over a target layer. A merge cut feature is formed in the mask layer. A first mandrel layer is formed over the mask layer...
US-9,818,612 Method for manufacturing semiconductor device
Disclosed is a method for manufacturing a semiconductor device. The method includes: a first pattern forming step of forming, on a pattern forming target film,...
US-9,818,611 Methods of forming etch masks for sub-resolution substrate patterning
Techniques disclosed herein provide a method for pitch reduction (increasing pitch/feature density) for creating high-resolution features and also for cutting...
US-9,818,610 Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)
A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a...
US-9,818,609 Epitaxial-silicon-wafer manufacturing method and epitaxial silicon wafer
A manufacturing method of an epitaxial silicon wafer including a silicon wafer doped with boron and having a resistivity of 100 m.OMEGA.cm or less and an...
US-9,818,608 Silicon carbide semiconductor substrate, method for manufacturing silicon carbide semiconductor substrate, and...
A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made...
US-9,818,607 Metal-induced crystallization of amorphous silicon in an oxidizing atmosphere
Techniques are provided for forming thin film transistors having a polycrystalline silicon active layer formed by metal-induced crystallization (MIC) of...
US-9,818,606 Amorphous silicon thickness uniformity improved by process diluted with hydrogen and argon gas mixture
The embodiments described herein generally relate to methods for forming an amorphous silicon structure that may be used in thin film transistor devices. In...
US-9,818,605 Oxide TFT, preparation method thereof, array substrate, and display device
An Oxide TFT, a preparation method thereof, an array substrate and a display device are described. The method includes forming a gate electrode, a gate...
US-9,818,604 Method for depositing insulating film on recessed portion having high aspect ratio
Provided is a method of depositing an insulation layer on a trench in a substrate, in which the trench having an aspect ratio of 5:1 or more is formed,...
US-9,818,603 Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing...
US-9,818,602 Method of depositing a resin material on a semiconductor body with an inkjet process
A method a described which includes depositing a first component of a multicomponent system by means of an inkjet process, and depositing a second component of...
US-9,818,601 Substrate processing apparatus and method of processing substrate
A substrate processing apparatus includes a chamber, a stage provided in the chamber, a shower head in which a plurality of slits are formed, and which is...
US-9,818,600 Substrate processing apparatus and method of manufacturing semiconductor device
A substrate processing apparatus includes: a plasma generating unit to excite a process gas into plasma state; a process chamber where a substrate is processed...
US-9,818,599 Method for in-situ dry cleaning, passivation and functionalization of Si--Ge semiconductor surfaces
A method for in-situ dry cleaning of a SiGe semiconductor surface doses the SiGe surface with ex-situ wet HF in a clean ambient environment or in-situ dosing...
US-9,818,598 Substrate cleaning method and recording medium
An object of the present invention is to be able to obtain a high removing performance of particles. The substrate processing method according to the exemplary...
US-9,818,597 Lucent waveguide plasma light source
A lucent waveguide plasma light source has a quartz waveguide body with a central through bore. The bore has orifices at its opposite ends, opening centrally of...
US-9,818,596 Arc lamp and substrate heating apparatus having the arc lamp
An arc lamp includes an arc tube configured to receive a reaction gas therein, and an anode and a cathode disposed opposite one another within the arc tube and...
US-9,818,595 Systems and methods for ion isolation using a dual waveform
A mass spectrometer includes a radio frequency ion trap; and a controller. The controller is configured to cause an ion population to be injected into the radio...
US-9,818,594 Integrated sample processing for electrospray ionization devices
Methods, systems and devices that generate differential axial transport in a fluidic device having at least one fluidic sample separation flow channel and at...
US-9,818,593 Radio-frequency ionization of chemicals
Methods and systems for performing ionization, including applying radio frequency energy to a chemical compound so that at least one ion of the compound or of a...
US-9,818,592 Ion guide or filters with selected gas conductance
Certain embodiments described herein are directed to rod assemblies such as, for example, quadrupole, hexapole and octupole rod assemblies. In some instances,...
US-9,818,591 Mirror lens for directing an ion beam
An electrostatic dual-mode lens assembly is provided for selectively transmitting or reflecting an ion beam in a mass spectrometer. The assembly comprises at...
US-9,818,590 Data quality after demultiplexing of overlapped acquisition windows in tandem mass spectrometry
Systems and methods are provided for identifying missing product ions after demultiplexing product ion spectra produced by overlapping precursor ion...
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