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Patent # Description
US-9,818,488 Read threshold voltage adaptation using bit error rates based on decoded data
A read threshold voltage for a memory is adjusted based on a bit error rate based on decoded data for a plurality of read threshold voltages. The read threshold...
US-9,818,487 Semiconductor memory device
A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A...
US-9,818,486 Fast secure erase in a flash system
A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a...
US-9,818,485 Nonvolatle memory device and memory system having the same, and related memory management, erase and...
An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation...
US-9,818,484 Systems, methods, and apparatus for memory cells with common source lines
Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a...
US-9,818,483 Row decoder and a memory device having the same
A row decoder of the semiconductor memory device includes a decoding and precharging unit that is connected between a high voltage node and a block word line,...
US-9,818,482 Volatile memory, memory module including the same, and method for operating the memory module
A memory module includes an emergency power supplier, a plurality of ranks each including one or more volatile memories, a non-volatile memory, and a controller...
US-9,818,481 Resistive memory device and operation method thereof
A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell...
US-9,818,480 Resistance change memory cell circuits and methods
The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current...
US-9,818,479 Switchable macroscopic quantum state devices and methods for their operation
Discloses is an electronic device and a method for its operation. The device has first and second electrodes and an active material. The active material has...
US-9,818,478 Programmable resistive device and memory using diode as selector
Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There...
US-9,818,477 Methods of programming memory cells in non-volatile memory devices
A method of operating a non-volatile memory device includes receiving program data and a program address. Memory cells that correspond to the program address...
US-9,818,475 Method of programming nonvolatile memory device
In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a...
US-9,818,474 Memory with keeper circuit
A memory device with a keeper circuit is disclosed herein. The memory device (i) improves current tracking between the device's memory cells and the keeper...
US-9,818,473 Semiconductor device including stacked circuits
This invention provides a semiconductor device with high speed operation and reduced size. A circuit includes a circuit including a memory circuit and a circuit...
US-9,818,472 Semiconductor device
A semiconductor device includes a plurality of memory cells being disposed in a matrix in a memory cell array area, each of the memory cells includes a...
US-9,818,471 Circuitry and methods for measuring and correcting duty-cycle distortion
A method of measuring duty-cycle distortion in a signal (e.g., flowing between an operating circuit and a memory circuit), where the signal has a known period,...
US-9,818,470 Multi-die memory device
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and...
US-9,818,469 Refresh control device and semiconductor device including the same
A refresh control device may include a command decoder configured to decode a command signal and a specific address, and output a refresh signal, an active...
US-9,818,468 Charge storage ferroelectric memory hybrid and erase scheme
A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each...
US-9,818,467 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: a first bit line; a first source line; a first word line; a first control line; a first...
US-9,818,466 Robust slope detection technique for STTRAM and MRAM sensing
Slope detection systems and methods are provided that monitor magnetic tunnel junction (MTJ) resistance switching. A low-overhead, sample-and-hold circuit can...
US-9,818,465 Self-referenced memory device and method using spin-orbit torque for reduced size
A self-referenced MRAM cell comprises a first portion of a magnetic tunnel junction including a storage layer; a second portion of the magnetic tunnel junction...
US-9,818,464 Magnetic memory element and memory device
According to one embodiment, a magnetic memory element includes a stacked structure. The stacked structure includes a first and a second stacked member. The...
US-9,818,463 Memory control component with inter-rank skew tolerance
In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the...
US-9,818,462 Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device
Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application....
US-9,818,461 Semiconductor memory device and operating method thereof
A semiconductor memory device includes a memory cell array; a memory cell array; a data receiver suitable for receiving a plurality of data sequentially...
US-9,818,460 Negative bitline write assist circuit and method for operating the same
A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write...
US-9,818,459 Invert operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,818,458 Techniques for entry to a lower power state for a memory device
Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device...
US-9,818,457 Extended platform with additional memory module slots per CPU socket
Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed...
US-9,818,456 Storage module installed with multiple M.2 SSDs
A storage module installed with multiple M.2 SSDs includes a frame, at least one circuit assembly, and plural M.2 SSDs. The circuit assembly is fixed to the...
US-9,818,455 Query operations for stacked-die memory device
An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies...
US-9,818,454 Hermetically-sealed data storage device for increased disk diameter
A data storage device involves inner surfaces of sidewalls of a second cover overlapping with and adhesively bonded with the outer surfaces of sidewalls of an...
US-9,818,453 Methods and devices for sealing hard drives
A hard drive includes a base deck with sidewalls to define a cavity. The hard drive further includes a weld lip that is positioned along and extends from the...
US-9,818,452 Rear pluggable hard disk drive with floating connecting mechanism
A hard disk drive carrier assembly includes a back panel, and a connection mechanism in physical communication with the back panel of the hard disk drive...
US-9,818,451 Frame selection of video data
A system and method for selecting portions of video data from preview video data is provided. The system may extract image features from the preview video data...
US-9,818,450 System and method of subtitling by dividing script text into two languages
A method of subtitling comprises the steps of obtaining an audio file of dialogue in a first language, obtaining a file of script text corresponding to the...
US-9,818,449 Editing method and recording and reproducing device
In order to provide a recording and reproducing device that allows a user to select and manage arbitrary play lists, a unit of management for managing all...
US-9,818,448 Media editing with linked time-based metadata
Systems and methods for linking time-based media and temporal metadata provide single command control during editing of media having associated temporal...
US-9,818,447 Measuring transition shifts due to laser power variation in a heat-assisted magnetic recording device
A method comprises writing a waveform on a magnetic recording medium using a heat-assisted magnetic recording apparatus which includes a laser. The method also...
US-9,818,446 File producing method, file producing device, and recording medium
A method according to one aspect of the present disclosure includes the steps of: acquiring a play list including identification information indicating each of...
US-9,818,445 Magnetic storage device readers
Implementations described and claimed herein includes a storage device comprising a plurality of readers, including a first subset of readers configured to read...
US-9,818,444 Information processing apparatus, control method thereof, and program
When displaying a plurality of reduced content items corresponding to original content items in a list, reduced content corresponding to original content being...
US-9,818,443 Magnetic recording medium having specific underlayer features
The magnetic recording medium has a nonmagnetic layer satisfying: the ratio of the total area accounted for by voids observed to the area of the observed region...
US-9,818,442 Magnetic media having improved magnetic grain size distribution and intergranular segregation
A method and system provide a magnetic recording media usable in a magnetic storage device. The magnetic recording media includes a substrate, at least one...
US-9,818,441 Thermally assisted magnetic recording medium and magnetic storage device
Disclosed is a thermally assisted magnetic recording medium comprising a substrate, a plurality of underlayers formed on the substrate, and a magnetic layer...
US-9,818,440 Heat assisted magnetic recording system having at least three possible magnetic configurations per physical bit
According to one embodiment, a heat assisted magnetic recording system includes a magnetic recording medium comprising a magnetic recording layer, where the...
US-9,818,439 Determining gamma of a read/write head based on active gain control and test signal amplitude measurements
A change in servo active gain control values is determined from a beginning of a writing of a test region of a recording medium to an end of the writing of the...
US-9,818,438 Skew compensation in a patterned medium
A system may compensate for skew in a patterned medium, such as but not limited to a self-assembling bit patterned medium, with a write pole separated from a...
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