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Patent # Description
US-9,824,950 Semiconductor device
A semiconductor device according to the invention includes an insulating substrate including an insulating plate, a circuit pattern that is formed on a front...
US-9,824,949 Packaging solutions for devices and systems comprising lateral GaN power transistors
Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a...
US-9,824,948 Integrated circuit with printed bond connections
A packaged integrated circuit is provided. The packaged integrated circuit includes a die, a package including a base, a lid, and a plurality of package leads,...
US-9,824,947 Through silicon via, scan cell stimulus, response to two switches
The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of...
US-9,824,946 Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level
A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of...
US-9,824,945 Semiconductor device and semiconductor device measuring method
A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance...
US-9,824,944 Semiconductor device
A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the...
US-9,824,943 Semiconductor structure and method for forming the same
A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of:...
US-9,824,942 Method of manufacturing thin-film transistor substrate including a copper alloy film
A method of manufacturing a thin-film transistor (TFT) substrate including a thin-film transistor having a CuMn alloy film. The method includes controlling a...
US-9,824,941 Systems and methods for detection of plasma instability by electrical measurement
A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode....
US-9,824,940 Intelligent metrology based on module knowledge
A method for intelligent inline metrology is a provided. A parameter of a workpiece is measured at a first set of inspection sites on the workpiece. A...
US-9,824,939 Semiconductor assembly and method to form the same
A semiconductor device having a composite pad including a primary portion and a subsidiary portion is disclosed. The primary portion is provided for electrical...
US-9,824,938 Charged particle beam device and inspection device
Provided is a charged particle beam device which can specify a position of an initial core with high accuracy even when fine line and space patterns are formed...
US-9,824,937 Flowable CVD quality control in STI loop
A method for semiconductor processing includes forming a first dielectric layer comprising an N-type dopant over a first plurality of fins extending above a...
US-9,824,936 Adjacent device isolation
An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a...
US-9,824,935 Methods of forming NMOS and PMOS FinFET devices and the resulting product
A method includes forming an initial strain relaxed buffer layer on a semiconductor substrate. A trench is formed within the initial strain relaxed buffer...
US-9,824,934 Shallow trench isolation recess process flow for vertical field effect transistor fabrication
A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a...
US-9,824,933 Stacked vertical-transport field-effect transistors
Structures and fabrication methods for a vertical-transport field-effect transistor. A plurality of pillars comprised of a semiconductor material are formed....
US-9,824,932 Method of making thermally-isolated silicon-based integrated circuits
Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material...
US-9,824,931 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon;...
US-9,824,930 Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme
A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly...
US-9,824,929 FinFET gate structure and method for fabricating the same
A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes...
US-9,824,928 Semiconductor device, related manufacturing method, and related electronic device
A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a PN junction with...
US-9,824,927 Methods for producing semiconductor devices
A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first...
US-9,824,926 Wafer processing method
A wafer is transferred to a holding surface of a chuck table by using a transfer unit having a suction pad. The front side of the wafer is held under suction...
US-9,824,925 Flip chip alignment mark exposing method enabling wafer level underfill
Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The...
US-9,824,924 Semiconductor packages having an electric device with a recess
Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess...
US-9,824,923 Semiconductor device and method of forming conductive pillar having an expanded base
A semiconductor device has a first semiconductor die and conductive vias in the first semiconductor die. The conductive vias can be formed by extending the vias...
US-9,824,922 Method of forming interconnect structures by self-aligned approach
A method includes forming a dielectric layer over a conductive feature. A first mask having a first opening is formed over the dielectric layer. A second mask...
US-9,824,921 Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric...
A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate...
US-9,824,920 Methods of forming self-aligned contact structures by work function material layer recessing and the resulting...
One method disclosed includes, among other things, forming a first plurality of gate cavities in a first dielectric layer. A work function material layer is...
US-9,824,919 Recess filling method and processing apparatus
There is provided a method of filling a recess with a germanium-based film composed of germanium or silicon germanium in a substrate to be processed on which an...
US-9,824,918 Method for electromigration and adhesion using two selective deposition
A method of manufacturing a semiconductor device includes providing a semiconductor substrate, sequentially forming an etch stop layer and an interlayer...
US-9,824,917 Method and apparatus for single chamber treatment
The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many...
US-9,824,916 Wiring structure and method of forming a wiring structure
A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure...
US-9,824,915 Structure for radiofrequency applications and process for manufacturing such a structure
The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the...
US-9,824,914 Method for manufacturing a device isolation structure
A method for forming a semiconductor device includes forming a buried doped layer in a semiconductor substrate and forming a plurality of first trenches that...
US-9,824,913 Isolation structure and manufacturing method thereof for high-voltage device in a high-voltage BCD process
The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation...
US-9,824,912 Method of transforming an electronic device
There is provided a method for transforming an electronic device from an initial state, wherein the device includes a first substrate and a second substrate,...
US-9,824,911 Substrate support and semiconductor manufacturing apparatus
A substrate support for supporting a substrate when forming a film on a surface of the substrate by chemical vapor deposition. The substrate support includes a...
US-9,824,910 Electrostatic chuck
An electrostatic chuck is disclosed. In one aspect, the electrostatic chuck includes a top plate, wherein first and second regions adjacent to each other are...
US-9,824,909 Chuck, in particular for use in a mask aligner
A chuck for aligning a first planar substrate in parallel to a second planar substrate includes a top plate having a top surface for arrangement of the first...
US-9,824,908 Conveying system, conveying robot and teaching method of the same
In this system, regarding an conveyance object placed on a rotary table, based on positions temporarily set previously as a taking position of the disk-shaped...
US-9,824,907 Gas purge apparatus, load port apparatus, and gas purge method
A gas purge apparatus, a load port apparatus, and a gas purge method are capable of filling a container with a cleaning gas without leaning the container to be...
US-9,824,906 Methods and structures for handling integrated circuits
In one embodiment, a tray that includes a dielectric frame structure, a re-adherable pad and a marking is disclosed. The dielectric frame structure includes a...
US-9,824,905 Semiconductor manufacturing device and semiconductor manufacturing method
A semiconductor manufacturing device has an upper cover configured to be arranged above top surface of unshielded semiconductor device which are mounted on a...
US-9,824,904 Method and apparatus for controlling spatial temperature distribution
A chuck for a plasma processor comprises a temperature-controlled base, a thermal insulator, a flat support, and a heater. The temperature-controlled base is...
US-9,824,903 Substrate cleaning apparatus
A substrate cleaning apparatus including a self-cleaning device is disclosed. The substrate cleaning apparatus includes a self-cleaning device configured to...
US-9,824,902 Integrated fan-out package and method of fabricating the same
An integrated fan-out package including a chip module, a second integrated circuit, a second insulating encapsulation, and a redistribution circuit structure is...
US-9,824,901 Complex cavity formation in molded packaging structures
Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial...
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