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Patent # Description
US-9,824,036 Memory systems with multiple modules supporting simultaneous access responsive to common memory commands
Described are memory systems in which a memory controller issues commands and addresses to multiple memory modules that collectively support each read and write...
US-9,824,035 Memory module with timing-controlled data paths in distributed data buffers
A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to...
US-9,824,034 Parallel ordering queue using encoded command types
Embodiments include method, systems and computer program products for a parallel ordering queue using an encoded command type. In some embodiments, a command...
US-9,824,033 Method and device of heap sorting based on a memory device
The present application relates to a heap sorting method based on arrangement and apparatus which can improve the heap sorting conducting speed through reducing...
US-9,824,032 Guest page table validation by virtual machine functions
Systems and methods for guest page table validation by virtual machine (VM) functions. An example method comprises: storing a first VM function invocation...
US-9,824,031 Efficient clearinghouse transactions with trusted and un-trusted entities
In an aspect of the present disclosure, a method is disclosed including receiving first transaction data from a first trusted party that includes a first...
US-9,824,030 Adjusting active cache size based on cache usage
Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device...
US-9,824,029 Memory device and operation method of the same
A memory device includes: a main block that includes a plurality of first pages that are accessible based on a multi-bit address; and a sub-block that includes...
US-9,824,028 Cache method and cache apparatus
A cache apparatus stores part of a plurality of accessible data blocks into a cache area. A calculation part calculates, for each pair of data blocks of the...
US-9,824,027 Apparatus, system, and method for a storage area network
An apparatus and system are disclosed for a storage area network ("SAN"). In one embodiment, a computer system includes an internal storage device and an...
US-9,824,026 Apparatus and method for managing a virtual graphics processor unit (VGPU)
An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic...
US-9,824,025 Information processing system, information processing device, information processing program and information...
An information processing system comprising a storage device and an information processing device, wherein the information processing device includes a data...
US-9,824,024 Configurable storage blocks with embedded first-in first-out and delay line circuitry
An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, an arithmetic circuit, and a control...
US-9,824,023 Management method of virtual-to-physical address translation system using part of bits of virtual address as index
A management method of a virtual-to-physical address translation system includes the following steps: providing a first storage space, wherein the first storage...
US-9,824,022 Address translation structures to provide separate translations for instruction fetches and data accesses
An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second...
US-9,824,021 Address translation structures to provide separate translations for instruction fetches and data accesses
An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second...
US-9,824,020 Systems and methods for memory management in a dynamic translation computer system
Systems and methods for managing memory in a dynamic translation computer system are provided. Embodiments may include receiving an instruction packet and...
US-9,824,019 Event specific page faults for interrupt handling
Various embodiments are generally directed to instrumenting an interrupt service routine. A non-executable address may be provisioned and added to an execution...
US-9,824,018 Systems and methods for a de-duplication cache
A de-duplication is configured to cache data for access by a plurality of different storage clients, such as virtual machines. A virtual machine may comprise a...
US-9,824,017 Cache control apparatus and method
Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data...
US-9,824,016 Device and processing method
A device includes, a memory, and, a processor coupled to the memory, including a cache memory, and configured, to hold a memory access instruction for executing...
US-9,824,015 Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and...
Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an...
US-9,824,014 Expedited servicing of store operations in a data processing system
In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is...
US-9,824,013 Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors
Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to...
US-9,824,012 Providing coherent merging of committed store queue entries in unordered store queues of block-based computer...
Providing coherent merging of committed store queue entries in unordered store queues of block-based computer processors is disclosed. In one aspect, a...
US-9,824,011 Method and apparatus for processing data and computer system
A method and an apparatus for processing data and a computer system are provided. The method includes copying a shared virtual memory page to which a first...
US-9,824,010 Multiple data channel memory module architecture
According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a...
US-9,824,009 Information coherency maintenance systems and methods
Systems and methods for coherency maintenance are presented. The systems and methods include utilization of multiple information state tracking approaches or...
US-9,824,008 Cache memory sharing in a multi-core processor (MCP)
This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A...
US-9,824,007 Data integrity enhancement to protect against returning old versions of data
Systems, methods and/or devices are used to enable enhancing data integrity to protect against returning old versions of data. In one aspect, the method...
US-9,824,006 Apparatus and system for object-based storage solid-state device
An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary...
US-9,824,005 Process level memory allocation by memory type
A leak detection system may be configured to receive a plurality of memory use reports periodically from a user device. The memory use reports may include an...
US-9,824,004 Methods and apparatuses for requesting ready status information from a memory
Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the...
US-9,824,003 Dynamically resizable circular buffers
Methods and apparatus for dynamically resizing circular buffers are described wherein circular buffers are dynamically allocated arrays from a pool of arrays....
US-9,824,002 Tracking of code base and defect diagnostic coupling with automated triage
In response to a test case error generated by execution of a test case against a code build, a source code segment that caused the test case error is identified...
US-9,824,001 System and method for steady state performance testing of a multiple output software system
This disclosure relates generally to software performance testing, and more particularly to a system and method for steady state performance testing of a...
US-9,824,000 Testing calling code dynamically with random error injection based on user-specified configuration
An apparatus includes a non-volatile storage medium and a processing circuit. The non-volatile storage medium stores code implementing an application program....
US-9,823,999 Program lifecycle testing
In one embodiment, a system for program lifecycle testing includes receiving a request to test a program update at an interface. Using a processor, the system...
US-9,823,998 Trace recovery via statistical reasoning
A method (and system) for trace recovery includes retrieving a code listing from a memory and performing a static analysis on the retrieved code listing. Based...
US-9,823,997 Production resiliency testing system
The present disclosure describes testing resiliency plans for applications on alternate hosts within production environments instead of simulated environments....
US-9,823,996 Debugging code for controlling intelligent devices using log data from executed object code
In some aspects, a debugging application can obtain log data from a target device. The log data can be generated from the execution of object code by the target...
US-9,823,995 Structured query language debugger
The present disclosure describes methods, systems, and computer program products for debugging structured query language (SQL) statements. One ...
US-9,823,994 Dynamically identifying performance anti-patterns
Dynamically identifying performance anti-patterns in a software system is based on a set of documented symptoms that are evaluated in real-time. The evaluation...
US-9,823,993 Preemptive trouble shooting using dialog manager
One or more problems may be detected in an executing application by retrieving runtime execution information from the application executing on one or more...
US-9,823,992 Decoupling dynamic program analysis from execution in virtual environments
Dynamic program analysis is decoupled from execution in virtual computer environments so that program analysis can be performed on a running computer program...
US-9,823,991 Concurrent workload simulation for application performance testing
Embodiments of the present invention provide a method, system and computer program product for concurrent workload simulation for application performance...
US-9,823,990 System and process for accounting for aging effects in a computing device
Embodiments of the claimed subject matter are directed to methods and systems that allow tracking and accounting of wear and other aging effects in integrated...
US-9,823,989 Method and apparatus for connecting to external device
An apparatus and method of connecting an external device are provided. The method includes connecting the apparatus to the external device when a distance...
US-9,823,988 System and method of test iteration via property chaining
A new test control structure improves on constructing complex test sequences in a scripting language. The new test control structure iterates over two or more...
US-9,823,987 Data quality pre-selection in read retry operations
Implementations disclosed herein provide a method comprising iteratively reading data from a failing media sector prior to a an error minimization operation,...
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