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Patent # Description
US-9,831,272 Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches
A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite...
US-9,831,271 Semiconductor device
A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact...
US-9,831,270 Nonvolatile semiconductor memory device and method for manufacturing the same
According to one embodiment, a nonvolatile semiconductor memory device includes first and second connectors, first and second conductive layers, a first...
US-9,831,269 Semiconductor device
According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first...
US-9,831,268 Ultrahigh density vertical NAND memory device and method of making thereof
A method of making a monolithic three dimensional NAND string is provided. A stack of alternating layers of a first material and a second material different...
US-9,831,267 Three-dimensional semiconductor device
A three-dimensional semiconductor device includes a plurality of stack structures extending in one direction on a substrate and spaced apart from each other, a...
US-9,831,266 Three-dimensional NAND device containing support pedestal structures for a buried source line and method of...
A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of...
US-9,831,265 Semiconductor device
Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes,...
US-9,831,264 Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed...
US-9,831,263 Semiconductor device including three dimensional memory string
A semiconductor device includes a semiconductor substrate divided into a first area and a second area, the semiconductor substrate including a first dopant of a...
US-9,831,262 Embedded HKMG non-volatile memory
The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small...
US-9,831,261 Semiconductor memory device with first and second semiconductor films in first and second columnar bodies
A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first...
US-9,831,260 Semiconductor memory devices
Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region...
US-9,831,259 Semiconductor device
Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating...
US-9,831,258 Semiconductor device and manufacturing method thereof
A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode...
US-9,831,257 SGVC 3D architecture with floating gate device in lateral recesses on sides of conductive strips and insulating...
A memory device is provided that includes a plurality of memory cells. The memory device includes a plurality of stacks of conductive strips separated by...
US-9,831,256 Semiconductor device and method for manufacturing same
A semiconductor device includes a base member, a first structure body, a second structure body, a first contact portion, a second contact portion, and a first...
US-9,831,255 Semiconductor device including an electrode lower layer and an electrode upper layer and method of...
A semiconductor device includes a lower electrode, a ferroelectric film on the lower electrode, an upper electrode on the ferroelectric film, and a first...
US-9,831,254 Multiple breakdown point low resistance anti-fuse structure
An anti-fuse structure is provided that contains multiple breakdown points which result in low resistance after the anti-fuse structure is blown. The anti-fuse...
US-9,831,253 FinFET memory device
A FinFET system comprises a first inverter comprising a first p-type pull-up transistor (PU) and a first n-type pull-down transistor (PD connected in series...
US-9,831,251 Method of fabricating semiconductor device and semiconductor device fabricated thereby
A method of fabricating a semiconductor device is disclosed. The method includes the steps of forming recesses in a semiconductor substrate; epitaxial growing a...
US-9,831,250 Static random access memory
A static random access memory (SRAM) cell includes first through fourth source diffusion regions sequentially arranged in a first direction, a first pass-gate...
US-9,831,249 Method of manufacturing semiconductor device and non-transitory computer-readable recording medium
A semiconductor manufacturing method includes preparing a substrate having a metal film formed on a surface thereof; forming an oxide layer by oxidizing a...
US-9,831,248 Embedded DRAM cells having capacitors within trench silicide trenches of a semiconductor structure
A semiconductor structure includes an array of fins extending horizontally across a substrate. A plurality of transistors are embedded in the fins. The...
US-9,831,247 Memory device comprising electrically floating body transistor
A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.
US-9,831,246 JFET device structures and methods for fabricating the same
In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a...
US-9,831,245 Complementary logic device using spin-orbit interaction difference and method for manufacturing the same
A complementary logic device includes i) a substrate, ii) a first semiconductor device located on the substrate and including a first channel layer, a carrier...
US-9,831,244 Method for manufacturing a semiconductor device
A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern...
US-9,831,243 Techniques providing metal gate devices with multiple barrier layers
A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain...
US-9,831,242 Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device, a doped layer is formed in a substrate. A barrier layer that is in contact with the doped layer is formed....
US-9,831,241 Method and structure for improving finFET with epitaxy source/drain
Isolation structures are formed to laterally surround a gate material block such that each sidewall of the gate material block abuts a corresponding sidewall of...
US-9,831,240 Elevated source drain semiconductor device with L-shaped spacers and fabricating method thereof
A semiconductor device includes a gate on a substrate, a gate insulating layer along a sidewall and a bottom surface of the gate, and an L-shaped spacer...
US-9,831,239 Negative capacitance FinFET device and manufacturing method of the same
Provided is a negative capacitance FinFET device including a FinFET device including a gate stack, a drain electrode and a source electrode formed on a...
US-9,831,238 Semiconductor device including insulating film having opening portion and conductive film in the opening portion
Provided is a semiconductor device that occupies a small area, a highly integrated semiconductor device, or a semiconductor device with high productivity. To...
US-9,831,236 Electrostatic discharge (ESD) protection transistor devices and integrated circuits with electrostatic...
An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction...
US-9,831,235 Method of making structure having a gate stack
A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a...
US-9,831,234 Electro-static discharge protection devices having a low trigger voltage
An electro-static discharge (ESD) protection device includes a first PN diode, a second PN diode and a silicon controlled rectifier (SCR). The first PN diode...
US-9,831,233 Apparatuses for communication systems transceiver interfaces
An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor...
US-9,831,232 ESD protection device
An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The...
US-9,831,231 ESD protection circuit with plural avalanche diodes
An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and...
US-9,831,230 Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a...
US-9,831,228 Opto-electronic apparatus and manufacturing method thereof
An opto-electronic apparatus and a manufacturing method thereof are disclosed. The manufacturing method of the opto-electronic apparatus includes the following...
US-9,831,227 Optoelectronic semiconductor apparatus and carrier assembly
A semiconductor apparatus with an optoelectronic device and a further device is disclosed. Embodiments of the invention provide a semiconductor apparatus with...
US-9,831,226 Optical coupling device, manufacturing method thereof, and power conversion system
In order to improve properties, an optical coupling device has a potting resin and an internal mold resin between a light emitting element and a light receiving...
US-9,831,225 Low-impedance power delivery for a packaged die
A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power...
US-9,831,224 Solution for reducing poor contact in info packages
A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding...
US-9,831,223 Flexible display apparatus and methods
A flexible display includes a plurality of pixel chips, chixels, provided on a flexible substrate. The chixels and the light emitters thereon may be shaped,...
US-9,831,222 Display device using semiconductor light emitting device and method for manufacturing the same
A display device including a substrate; a first electrode on the substrate; and a plurality of semiconductor light emitting devices disposed on the first...
US-9,831,221 Light emitting device package and lighting apparatus including the same
A light emitting device package includes: a light emitting device disposed on a substrate; a diffusion plate disposed on the substrate to surround the light...
US-9,831,220 Light emitting diode (LED) arrays including direct die attach and related assemblies
An electronic device may include a packaging substrate having a packaging face, and the packaging substrate may include positive and negative electrically...
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