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Patent # Description
US-9,831,219 Manufacturing method of package structure
A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is...
US-9,831,218 Wafer to wafer stacking
Embodiments herein describe techniques for wafer to wafer stacking of integrated circuit chips (e.g., dice) to form stacked IC devices. In one example, a...
US-9,831,217 Method of fabricating package substrates
This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier...
US-9,831,216 Chip packaging module
The present disclosure discloses a chip packaging module, including: a first chip, where a first pad is disposed on a side neighboring to a front surface of the...
US-9,831,215 Semiconductor package and forming method thereof
A semiconductor package includes at least one first semiconductor device, a first molding compound, a dielectric layer, at least one conductive feature and at...
US-9,831,214 Semiconductor device packages, packaging methods, and packaged semiconductor devices
Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device...
US-9,831,213 Bumpless build-up layer package with pre-stacked microelectronic devices
The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL)...
US-9,831,212 Semiconductor device
An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor...
US-9,831,211 Anisotropic conductive material, electronic device including anisotropic conductive material, and method of...
Provided are anisotropic conductive materials, electronic devices including anisotropic conductive materials, and/or methods of manufacturing the electronic...
US-9,831,210 Electronic device and electronic apparatus
An electronic device includes an electrode including Cu, a solder including Sn and provided above the electrode, and a joining layer including In and Ag and...
US-9,831,209 Semiconductor device
Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main...
US-9,831,208 Driving chip and display device
A driving chip and a display device, relating to the technical field of driving chip for displays, are disclosed. A surface of the driving chip has a first edge...
US-9,831,207 No-flow underfill for package with interposer frame
A method of forming a package on a package structure includes applying a no-reflow underfill (NUF) layer over a substrate, wherein the substrate has at least...
US-9,831,206 LPS solder paste based low cost fine pitch pop interconnect solutions
Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the...
US-9,831,205 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a...
US-9,831,204 Semiconductor device with a semiconductor chip connected in a flip chip manner
A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional...
US-9,831,203 Electronic component package and electronic device including the same
An electronic component package includes an electronic component, a redistribution layer electrically connected to the electronic component and having terminal...
US-9,831,202 Semiconductor devices with solder-based connection terminals and method of forming the same
An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection...
US-9,831,201 Methods for forming pillar bumps on semiconductor wafers
The subject matter contained herein discloses methods for forming a vertical metallic pillar overlying an under bump metal pad further overlying a semiconductor...
US-9,831,200 Package with passive devices and method of forming the same
An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device...
US-9,831,198 Inductors for integrated voltage regulators
An active component of an integrated voltage regulator (IVR) circuit is deployed within an IC device for regulating an operating voltage thereof. An interposer...
US-9,831,197 Wafer-level package with metal shielding structure and the manufacturing method thereof
Provided is a wafer-level package with metal shielding structure and the manufacturing method for producing the same. The wafer-level package includes first...
US-9,831,196 Methods and apparatus of guard rings for wafer-level-packaging
A method of forming a semiconductor device includes forming a passivation layer on top of a guard ring and an active area of a circuit device, forming a...
US-9,831,195 Semiconductor package structure and method of manufacturing the same
Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second...
US-9,831,194 Edge compression layers
Structures for a chip, as well as methods of fabricating such chip structures. The chip including a portion of a substrate, an active circuit region associated...
US-9,831,193 Methods and apparatus for scribe street probe pads with reduced die chipping during wafer dicing
An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes....
US-9,831,192 Cavity formation in semiconductor devices
Fabricating of radio-frequency (RF) devices involve providing a field-effect transistor (FET) formed over an oxide layer formed on a semiconductor substrate,...
US-9,831,191 Electronic package, semiconductor substrate of the electronic package, and method for manufacturing the...
A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one...
US-9,831,190 Semiconductor device package with warpage control structure
Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage...
US-9,831,189 Integrated circuit package with a conductive grid formed in a packaging substrate
An integrated circuit package includes a packaging substrate, which has an electrically conductive grid formed on a dielectric layer, and an integrated circuit...
US-9,831,188 Noise cancellation for a magnetically coupled communication link utilizing a lead frame
An integrated circuit package includes an encapsulation and a lead frame with a portion of the lead frame disposed within the encapsulation. The lead frame...
US-9,831,187 Apparatus and method for electrostatic spraying or electrostatic coating of a thin film
Provided is a resist film forming device which uses an electrostatic spray device which is capable of forming a thin film with a uniform thickness on a...
US-9,831,186 Methods of manufacturing semiconductor devices using alignment marks to align layers
A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark...
US-9,831,185 Chip package and fabrication method thereof
A chip package includes a chip, a laser stop layer, a first through hole, an isolation layer, a second through hole and a conductive layer. The laser stop layer...
US-9,831,184 Buried TSVs used for decaps
An interposer having decaps formed in blind-vias, a packaged semiconductor structure having decaps formed in blind-vias, and methods for forming the same are...
US-9,831,183 Contact structure and method of forming
Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an...
US-9,831,182 Multiple pre-clean processes for interconnect fabrication
A method of making an interconnect structure includes forming an opening within a dielectric material layer disposed on a substrate including a conductive...
US-9,831,181 Simultaneous formation of liner and metal conductor
An integrated circuit device having a substrate including a dielectric layer is patterned with a set of conductive line trenches. Each conductive line trench...
US-9,831,180 Semiconductor device and method for manufacturing same
According to the embodiment, the semiconductor device includes: a substrate; a stacked body; and a plurality of columnar portions. The stacked body is provided...
US-9,831,179 Semiconductor device and method of manufacturing a semiconductor device
A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width...
US-9,831,178 Display substrate, manufacturing method thereof and display device
A display substrate comprises a base substrate and a first metal layer, a second metal layer, a first electrode pattern, a second electrode pattern, a first...
US-9,831,177 Through via structure
An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via...
US-9,831,176 Semiconductor integrated circuit device and method of manufacturing the same
A semiconductor integrated circuit device includes a fuse element that can be laser trimmed to adjust the characteristics of the semiconductor integrated...
US-9,831,175 Method, apparatus, and system for E-fuse in advanced CMOS technologies
Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an...
US-9,831,174 Devices and methods of forming low resistivity noble metal interconnect
Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance:...
US-9,831,173 Slot-shielded coplanar strip-line compatible with CMOS processes
A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the...
US-9,831,172 Semiconductor devices having expanded recess for bit line contact
A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and...
US-9,831,171 Capacitors with barrier dielectric layers, and methods of formation thereof
A device including a first metal feature is disposed in a first insulating layer. A second metal feature is disposed in a second insulating layer and separated...
US-9,831,170 Fully molded miniaturized semiconductor module
A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads,...
US-9,831,169 Integrated circuit package substrate
Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment...
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