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Patent # Description
US-9,831,168 Electrical connectivity of die to a host substrate
According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A...
US-9,831,167 Compound carrier board structure of flip-chip chip-scale package and manufacturing method thereof
A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with an opening bonded to a carrier...
US-9,831,166 Semiconductor device
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a...
US-9,831,165 Interposer substrate and method of manufacturing the same
A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive...
US-9,831,164 Semiconductor device and method of fabricating the same
A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The...
US-9,831,163 Circuit substrate and method for manufacturing the same
A circuit substrate includes a core substrate having a cavity, a metal block accommodated in the cavity of the core substrate, a first build-up layer including...
US-9,831,162 Semiconductor device comprising a semiconductor chip mounted over a metal plate having an inclined surface
An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first...
US-9,831,161 Support terminal integral with die pad in semiconductor package
A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first...
US-9,831,160 Semiconductor device
A semiconductor device includes: opposed first and second metal plates; a plurality of semiconductor elements each interposed between the first metal plate and...
US-9,831,159 Semiconductor package with embedded output inductor
In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first...
US-9,831,158 Lead frame and semiconductor device
A semiconductor device includes a lead frame; a semiconductor chip mounted on the lead frame; and an encapsulation resin, wherein a convexo-concave portion...
US-9,831,157 Method of attaching an electronic part to a copper plate having a surface roughness
In a method for producing an electronic part mounting substrate wherein an electronic part 14 is mounted on one major surface (a surface to which the electronic...
US-9,831,156 Front-to-back bonding with through-substrate via (TSV)
Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer. A...
US-9,831,155 Chip package having tilted through silicon via
A chip package includes at least one integrated circuit die. The integrated circuit die includes a substrate portion having an internal plane between a front...
US-9,831,154 Semiconductor structure and manufacuting method of the same
The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in...
US-9,831,153 Heat dissipating device
A heat dissipating device is provided for reducing the high production costs of conventional heat dissipating devices. The heat dissipating device is mounted on...
US-9,831,152 Semiconductor device
A control terminal 14 of a semiconductor device has a recessed portion 14c. A resin case 15 is provided with a fixing member 152 engaging with and fixing a...
US-9,831,151 Heat sink for semiconductor modules
A thermal interface includes a first thermal interface material (TIM) layer and a lid disposed on the first TIM layer. A second TIM layer is disposed on a...
US-9,831,150 Semiconductor device and electronic device
According to one embodiment, a semiconductor device includes a first substrate, a second substrate, a first electronic component, a heat-conducting layer, a...
US-9,831,149 Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity...
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed...
US-9,831,148 Integrated fan-out package including voltage regulators and methods forming same
A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and...
US-9,831,147 Packaged semiconductor device with internal electrical connections to outer contacts
In an embodiment, an electronic component includes a first dielectric layer including an organic component having a decomposition temperature of at least...
US-9,831,146 Molded package
A molded package includes an IC chip mounted on a first surface of a lead frame, and a molded resin encapsulating the lead frame together with the IC chip. The...
US-9,831,145 Semiconductor device, and alternator and power converter using the semiconductor device
Provided is a semiconductor device including: a first external electrode which includes a circular outer peripheral portion; a MOSFET chip; a control circuit...
US-9,831,144 Semiconductor die and package jigsaw submount
A submount for connecting a semiconductor device to an external circuit, the submount comprising: a planar substrate formed from an insulating material and...
US-9,831,143 Air cavity package
A leadframe and air cavity packages formed using the leadframe are described. Using the leadframe, several air cavity packages can be quickly formed at one...
US-9,831,142 Board for electronic component package, electronic component package, and method of manufacturing board for...
A board for an electronic component package includes a wiring part on which an electronic component is disposed, wherein the wiring part includes an insulating...
US-9,831,141 Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements ("NCEM"). Such...
US-9,831,140 Wafer having pad structure
A wafer including a substrate having a plurality of integrated circuits formed above the substrate, and at least one scribe line between two of the integrated...
US-9,831,139 Test structure and method of manufacturing structure including the same
A test structure for manufacturing a semiconductor device includes a test element, a first pad connected to the test element, and a second pad connected to the...
US-9,831,138 Display substrate, method of testing the display substrate and display apparatus having the display substrate
A display substrate includes a first gate line configured to receive a first gate clock, a second gate line adjacent to the first gate line and configured to...
US-9,831,137 Defect imaging apparatus, defect detection system having the same, and method of detecting defects using the same
The defect imaging apparatus including a chamber having a stage to which a substrate having at least one process defect and at least one reference defects...
US-9,831,136 Film thickness metrology
Methods for determining a target thickness of a conformal film with reduced uncertainty, and an integrated circuit (IC) chip having a conformal film of the...
US-9,831,135 Method of forming a biCMOS semiconductor chip that increases the betas of the bipolar transistors
The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a...
US-9,831,134 Method of manufacturing a semiconductor device having deep wells
A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation...
US-9,831,133 Semiconductor devices having metal gate and method for manufacturing semiconductor devices having metal gate
A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided....
US-9,831,132 Methods for forming fin structures
A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing...
US-9,831,131 Method for forming nanowires including multiple integrated devices with alternate channel materials
Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first stack...
US-9,831,130 Method for forming semiconductor device structure
A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack, a second gate stack, and a third gate stack,...
US-9,831,129 Semiconductor device manufacturing method
A semiconductor device manufacturing method which improves working efficiency. The method includes the step of transporting by air a package as a sealed...
US-9,831,128 Method of processing a substrate
The invention relates to a method of processing a substrate, having a first surface with at least one division line formed thereon and a second surface opposite...
US-9,831,127 Method of processing a semiconductor substrate and semiconductor chip
A method of processing a semiconductor substrate is provided. The method may include forming a film over a first side of a semiconductor substrate, forming at...
US-9,831,126 Method of manufacturing semiconductor device, semiconductor substrate, and semiconductor device
A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate including a semiconductor layer having a first main...
US-9,831,125 Method for manufacturing semiconductor device
According to one embodiment, a method for manufacturing a semiconductor device includes forming a silicon film on an upper surface side, a lower surface side,...
US-9,831,124 Interconnect structures
The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure...
US-9,831,123 Methods of forming MIS contact structures on transistor devices
One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a...
US-9,831,122 Integrated circuit including wire structure, related method and design structure
An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on...
US-9,831,121 Semiconductor memory device with contact plugs extending inside contact connection portions
According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction....
US-9,831,120 Semiconductor arrangement and method of making the same
One or more semiconductor arrangements are provided. A semiconductor arrangement includes a first dielectric layer defining a first recess, a first contact in...
US-9,831,119 Semiconductor device and method of fabricating the same
A method of fabricating a semiconductor device is provided as follows. An epitaxial layer is formed on an active fin structure. Metal gate electrodes are formed...
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