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Patent # Description
US-9,830,305 Interface definition language extensions
Various embodiments provide an interface between a Web browser's layout engine and a scripting engine. The interface enables objects from the layout engine to...
US-9,830,304 Systems and methods for integrating dynamic content into electronic media
Embodiments of the invention provide methods and supporting systems for programmatically inserting highly-relevant content ("inserted content" or "display...
US-9,830,303 Optimized matrix multiplication using vector multiplication of interleaved matrix values
The present disclosure relates to optimized matrix multiplication using vector multiplication of interleaved matrix values. Two matrices to be multiplied are...
US-9,830,302 Sparse matrix vector multiplication
Systems and methods for multiplying a sparse matrix by a vector using a single instruction multiple data (SIMD) architecture are provided. An example method...
US-9,830,301 Predictive service requirement estimation for photovoltaic arrays
A method of determining whether service is needed on a solar array includes gathering current data with regard to current solar array performance and...
US-9,830,300 Hybrid programmable many-core device with on-chip interconnect
The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core...
US-9,830,299 Method for selecting shapes in a graphical display
A selector shape may serve as the background to a configurable composite shape and may include one or more expressions that are evaluated to select between...
US-9,830,298 Media time based USB frame counter synchronization for Wi-Fi serial bus
A method of transmitting universal serial bus (USB) frames over a communications channel is disclosed. A USB device receives one or more USB frames from a host...
US-9,830,297 Processor system for control of modular autonomous system
A cubesat communications system includes an on-board computer implemented on a hardware platform. The on-board computer may include a system on module having a...
US-9,830,296 Information processing apparatus, information processing method, and program
An information processing apparatus including processing units and a connection control unit that controls the connections between the processing units, in...
US-9,830,295 Resource domain partioning in a data processing system
A resource domain controller in a data processing system stores information that is used to group various resources, such as bus masters and peripherals, into...
US-9,830,294 Data processing system and method for handling multiple transactions using a multi-transaction request
A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of...
US-9,830,293 Information processing apparatus, storage system, and computer-readable non-transitory storage medium storing...
An information processing apparatus includes: an interface unit that communicates with another device through a plurality of physical links; a setting unit that...
US-9,830,292 Architected protocol for changing link operating mode
In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link...
US-9,830,291 Connecting device, method for the operation thereof, and bus communication device
A connecting device (27) has a first connection input (28), a second connection input (29), and a connection output (30). The two connection inputs (28, 29) are...
US-9,830,290 Image sharing system and method thereof
An image sharing system includes a first electronic device, a number of second electronic devices in wireless communication with the first electronic device,...
US-9,830,289 Methods and apparatus for aggregating packet transfer over a virtual bus interface
Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments...
US-9,830,288 System and method for transmitting graphics rendered on a primary computer to a secondary computer
One embodiment of the present invention sets forth a method for transmitting data rendered on a primary computer to a secondary computer. The method includes...
US-9,830,287 Determination of a device function asserting a detected spurious interrupt
Systems and methods are provided for detection of device functions asserting a spurious interrupt. An example method includes detecting, by a central processing...
US-9,830,286 Event signaling in virtualized systems
A method and system for permitting a guest to program a message-signaled interrupt-based device is disclosed. A hypervisor of a host detects a request by a...
US-9,830,285 Memory mapping in a processor having multiple programmable units
The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has...
US-9,830,284 Memory mapping in a processor having multiple programmable units
The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has...
US-9,830,283 Multi-mode agent
According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the...
US-9,830,282 Embedded storage device including a plurality of storage units coupled via relay bus
An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave...
US-9,830,281 Semiconductor device and electronic device
A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first...
US-9,830,280 Multiple access single SDIO interface with multiple SDIO units
A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed....
US-9,830,279 Interconnection of peripheral devices on different electronic devices
A peripheral device connected to a local electronic device which is connected to at least one communication network can communicate with a peripheral device...
US-9,830,278 Tracking replica data using key management
Source and replica data in a storage area network is tracked during management of data encryption keys. Association of source and replica data allows for all...
US-9,830,277 Selective space reclamation of data storage memory employing heat and relocation metrics
Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining...
US-9,830,276 Replaying memory transactions while resolving memory access faults
One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay...
US-9,830,275 Translation lookaside buffer
Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support virtualization and multi-threading....
US-9,830,274 Caching and deduplication of data blocks in cache memory
Techniques for deduplicating data in cache memory include determining that a first data block stored in the cache memory matches a second data block stored in...
US-9,830,273 Deduplicated host cache flush to remote storage
In addition to caching I/O operations at a host, at least some data management can migrate to the host. With host side caching, data sharing or deduplication...
US-9,830,272 Cache memory staged reopen
An apparatus is described. The apparatus includes a cache memory having two or more memory blocks and a central processing unit (CPU), coupled to the cache...
US-9,830,271 Transparent virtualization of cloud storage
Embodiments present a virtual disk image to applications such as virtual machines (VMs) executing on a computing device. The virtual disk image corresponds to...
US-9,830,270 Optimized memory layout through data mining
A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted...
US-9,830,269 Methods and systems for using predictive cache statistics in a storage system
Method and systems for a storage system are provided. Simulated cache blocks of a cache system are tracked using cache metadata while performing a workload...
US-9,830,268 Arithmetic processing device for disabling an unnecessary prefetch command and control method of arithmetic...
An arithmetic processing device includes a decoder which decodes commands, a command holding unit configured to register therein the commands involving memory...
US-9,830,267 Continuous page read for memory
Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.
US-9,830,266 Techniques for data prefetching
Described are techniques for processing a data operation in a data storage system. A front-end component of the data storage system receives the data operation....
US-9,830,265 Reuse of directory entries for holding state information through use of multiple formats
The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can...
US-9,830,264 Cache memory system and operating method for the same
A cache memory system includes a cache memory, which stores cache data corresponding to portions of main data stored in a main memory and priority data...
US-9,830,263 Cache consistency
A computer-executable method, system, and computer program product for managing a data storage system using a distributed write-through cache, wherein the data...
US-9,830,261 Region descriptor management method and electronic apparatus thereof
A region descriptor management method and an electronic apparatus are provided. The region descriptor management method is adapted to a device controller of the...
US-9,830,260 Method for mapping page address based on flash memory and system therefor
The present invention relates to a method for a page-level address mapping based on flash memory and a system thereof. A method for a page-level address mapping...
US-9,830,259 System and method for selecting victim memory block for garbage collection
Embodiments of present disclosure disclose method and system for selecting victim memory block for garbage collection. A memory block having minimum valid unit...
US-9,830,258 Storage system
A storage system monitors the first access frequency of occurrence which is the access frequency of occurrence from a host device during a first period, and the...
US-9,830,257 Fast saving of data during power interruption in data storage systems
Embodiments of systems and methods that ensure integrity of data during unexpected power interruption of loss are disclosed. In some embodiments, critical data...
US-9,830,256 Block device workload analysis
Techniques are described for formally expressing whether sequences of operations performed on block storage devices are sequential or random. In embodiments,...
US-9,830,255 System and method for optimizing test suite comprising plurality of test cases
The present disclosure relates to a method for optimizing test suite comprising plurality of test cases. The method comprises receiving, a test suite comprising...
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