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Patent # Description
US-9,842,952 Photovoltaic cell module and method of forming
A photovoltaic cell module, a photovoltaic array including at least two modules, and a method of forming the module are provided. The module includes a first...
US-9,842,951 Encapsulants for photovoltaic modules
A photovoltaic (PV) Module can include a substantially transparent cover, first encapsulant, a solar cell and a second encapsulant. The second encapsulant can...
US-9,842,950 Solar cell module apparatus and method of fabricating the same
Disclosed are a solar cell module apparatus and a method of fabricating the same. The solar cell module apparatus includes a light absorbing layer, and a...
US-9,842,949 High-efficiency solar photovoltaic cells and modules using thin crystalline semiconductor absorbers
Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical...
US-9,842,948 Solar cell
An solar cell is provided comprising a photoelectric conversion layer formed on a substrate formed of a semiconductor material, and a first finger electrode...
US-9,842,947 Photoconversion device with enhanced photon absorption
A photovoltaic device cell comprising a first light transmissive electrical contact, an active region, a second light transmissive electrical contact, and a...
US-9,842,946 Semiconductor device comprising an emitter of radiation and a photosensor and appertaining production method
The semiconductor device comprises a semiconductor substrate (1), a photosensor (2) integrated in the substrate (1) at a main surface (10), an emitter (12) of...
US-9,842,945 Photovoltaic module with flexible circuit
A photovoltaic module, and method of making, is disclosed in which a flexible circuit is electrically coupled to a plurality of photovoltaic cells, where the...
US-9,842,944 Solid-source diffused junction for fin-based electronics
A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is...
US-9,842,943 Method for manufacturing semiconductor device
Provided is a method for manufacturing a semiconductor device including a film to be treated having a high flatness. A semiconductor substrate having a surface...
US-9,842,942 Semiconductor device and method for manufacturing the same
An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even...
US-9,842,941 Semiconductor device and manufacturing method thereof
A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having low off-state...
US-9,842,940 Semiconductor device
A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over...
US-9,842,939 Semiconductor device
In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate...
US-9,842,938 Semiconductor device and display device including semiconductor device
A semiconductor device includes a transistor which includes a first gate electrode, a first insulating film, an oxide semiconductor film, source and drain...
US-9,842,937 Semiconductor device having an oxide semiconductor film and a metal oxide film
The oxide semiconductor film has the top and bottom surface portions each provided with a metal oxide film containing a constituent similar to that of the oxide...
US-9,842,935 Low temperature poly silicon (LTPS) thin film transistor (TFT) and the manufacturing method thereof
The present disclosure discloses a LTPS TFT and the manufacturing method thereof. The method includes: forming a semiconductor layer and a LTPS layer on the...
US-9,842,934 Array substrate and method of fabricating the same
A method of manufacturing an array substrate is discussed. The method includes forming a gate line on a substrate including a pixel region, forming a gate...
US-9,842,933 Formation of bottom junction in vertical FET devices
Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor...
US-9,842,932 FinFET with P/N stacked fins and method for fabricating the same
A semiconductor device is provided and includes a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin includes plural pairs of...
US-9,842,931 Self-aligned shallow trench isolation and doping for vertical fin transistors
A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off...
US-9,842,930 Semiconductor device and fabrication method thereof
A semiconductor device includes a first gate stack and a second gate stack over a substrate, an isolation structure in the substrate, a first epitaxial (epi)...
US-9,842,929 Strained silicon complementary metal oxide semiconductor including a silicon containing tensile N-type fin...
A method of forming a semiconductor device that includes forming a strain relaxed buffer (SRB) layer atop a supporting substrate, and epitaxially forming a...
US-9,842,928 Tensile source drain III-V transistors for mobility improved n-MOS
An n-MOS transistor device and method for forming such a device are disclosed. The n-MOS transistor device comprises a semiconductor substrate with one or more...
US-9,842,927 Integrated circuit structure without gate contact and method of forming same
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate...
US-9,842,926 Method for producing semiconductor device and semiconductor device
A semiconductor device includes a pillar-shaped semiconductor layer and a first gate insulating film around the pillar-shaped semiconductor layer. A metal gate...
US-9,842,925 Insulated gate semiconductor device having a shield electrode structure and method
A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, the junction blocking region having a lower...
US-9,842,924 Semiconductor device having an electrode that is in a peripheral trench region and at a same potential as a...
A semiconductor device includes a layer having first and second surfaces, a first region including central and peripheral portions, and a second region on the...
US-9,842,923 Ohmic contact structure for semiconductor device and method
In one embodiment, a high electron mobility device structure includes heterostructure with a Group III-nitride channel layer and a Group III-nitride barrier...
US-9,842,922 III-nitride transistor including a p-type depleting layer
A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further...
US-9,842,921 Direct tunnel barrier control gates in a two-dimensional electronic system
A quantum semiconductor device is provided. The quantum semiconductor device includes a quantum heterostructure, a dielectric layer, and an electrode. The...
US-9,842,920 Gallium nitride semiconductor device with isolated fingers
Implementations of semiconductor devices may include: an isolated drain finger, a gate ring, and a source ring; wherein the gate ring surrounds a perimeter of...
US-9,842,919 Semiconductor device
A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The...
US-9,842,918 Semiconductor device and method for producing the same
A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace...
US-9,842,917 Methods of operating power semiconductor devices and structures
Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite...
US-9,842,916 Oxide semiconductor layer and production method therefor, oxide semiconductor precursor, oxide semiconductor...
The invention provides an oxide semiconductor layer that has less cracks and is excellent in electrical property and stability, as well as a semiconductor...
US-9,842,915 Array substrate for liquid crystal display device and method of manufacturing the same
An array substrate for a liquid crystal display device includes a substrate; a semiconductor layer on the substrate; a gate electrode on the semiconductor...
US-9,842,914 Nanosheet FET with wrap-around inner spacer
A method of forming a semiconductor device and resulting structures having stacked nanosheets with a wrap-around inner spacer by forming a nanosheet stack...
US-9,842,913 Integrated circuit fabrication with boron etch-stop layer
Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich...
US-9,842,912 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a...
US-9,842,911 Adaptive charge balanced edge termination
In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer...
US-9,842,910 Methods for manufacturing devices with source/drain structures
In a method, a gate structure is formed over a substrate, and source/drain (S/D) features are formed in the substrate and interposed by the gate structure. At...
US-9,842,909 Semiconductor device and fabricating method thereof
A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect...
US-9,842,908 Method of manufacturing semiconductor device that includes forming junction field effect transistor including...
A method of manufacturing a semiconductor device that includes a junction field effect transistor, the junction field effect transistor including a ...
US-9,842,907 Memory device containing cobalt silicide control gate electrodes and method of making thereof
An alternating stack of insulating layers and sacrificial material layers can be formed over a substrate. Memory stack structures and a backside trench are...
US-9,842,906 Semiconductor device
A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n.sup.+-source region formed in an upper portion of an n.sup.--drift layer....
US-9,842,905 Semiconductor device and method for fabricating the same
A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a...
US-9,842,904 Method of manufacturing a semiconductor device having a trench at least partially filled with a conductive...
A method of manufacturing a semiconductor device includes forming a first trench in a semiconductor substrate from a first side, forming a semiconductor layer...
US-9,842,903 Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating...
Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An...
US-9,842,902 Method for producing surrounding gate semiconductor device
An SGT is produced by forming a first insulating film around a fin-shaped semiconductor layer, forming a pillar-shaped semiconductor layer in an upper portion...
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