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Patent # Description
US-9,842,848 Embedded HKMG non-volatile memory
The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small...
US-9,842,847 Drain select gate formation methods and apparatus
Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate...
US-9,842,846 Semiconductor device and method of manufacturing the same
In a semiconductor substrate, a memory cell region in which a flash memory cell is formed is defined by an element isolation region. A floating gate electrode...
US-9,842,845 Method of forming a semiconductor device structure and semiconductor device structure
The present disclosure provides a semiconductor device structure including a non-volatile memory (NVM) device structure in and above a first region of a...
US-9,842,844 Contact strap for memory array
Devices and methods for forming a device are disclosed. The method includes providing a substrate having a memory array region. Front end of line (FEOL) process...
US-9,842,843 Method for manufacturing static random access memory device
In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall...
US-9,842,842 Semiconductor memory device and semiconductor device and electronic device having the same
A memory cell includes a node and first transistor to third transistors. The third transistor and the second transistor are electrically connected to a fourth...
US-9,842,841 Semiconductor device and method of fabricating the same
A method of fabricating a semiconductor device, the method including etching a portion of a substrate including a first region and a second region to form a...
US-9,842,840 Transistors and memory arrays
Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post...
US-9,842,839 Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array...
A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material....
US-9,842,838 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench;...
US-9,842,837 Semiconductor device
Disclosed is a semiconductor device including a plurality of conductive patterns formed on a semiconductor substrate while being spaced apart from one another...
US-9,842,836 Diode
A diode according to the present invention includes a semiconductor layer of a first conductivity type having an impurity concentration of 1.times.10.sup.16...
US-9,842,835 High density nanosheet diodes
Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and...
US-9,842,834 Horizontal current bipolar transistors with improved breakdown voltages
A horizontal current bipolar transistor comprises a substrate of first conductivity type, defining a wafer plane parallel to said substrate; a collector drift...
US-9,842,833 Electrostatic discharge protection
A chip includes a first die, a second die, a first and a second through-silicon vias, a first protection circuit, and a second protection circuit. The first die...
US-9,842,832 High density interconnection of microelectronic devices
A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically...
US-9,842,831 Semiconductor package and fabrication method thereof
A semiconductor package includes a semiconductor die having an active surface and a bottom surface opposite to the active surface; a plurality of bond pads...
US-9,842,830 Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and...
A package can include first and second semiconductor devices stacked in a first direction. The first semiconductor device can include a first circuit formed on...
US-9,842,829 Chip package structure and method for forming the same
A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip package stacked over the...
US-9,842,828 Stacked semiconductor package with compliant corners on folded substrate
One or more embodiments are directed to stacked packages, such as Package-on-Package (PoP) packages, that are stacked on a flexible folded substrate. The...
US-9,842,827 Wafer level system in package (SiP) using a reconstituted wafer and method of making
A package such as a system in package (SiP) includes a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the first...
US-9,842,826 Semiconductor device and method of manufacture
An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the...
US-9,842,825 Substrateless integrated circuit packages and methods of forming same
Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed...
US-9,842,824 Component mounting apparatus
A component mounting apparatus crimps a component to a transparent substrate. The component is mounted on the transparent substrate through a photo-modifiable...
US-9,842,823 Chip-stacking apparatus having a transport device configured to transport a chip onto a substrate
A chip-stacking apparatus for stacking a chip on a substrate is provided. The chip-stacking apparatus includes a substrate support configured to carry the...
US-9,842,822 Semiconductor packages with socket plug interconnection structures
A semiconductor package may include a first substrate and a second substrate. Socket bumps may be disposed on the first substrate to provide insertion grooves...
US-9,842,821 Semiconductor device including semiconductor chip, wiring, conductive material, and contact part
A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different...
US-9,842,820 Wafer-level fan-out wirebond packages
An integrated circuit package that includes an integrated circuit die, a redistribution substrate, a wirebond interconnect and a package substrate is disclosed....
US-9,842,819 Tall and fine pitch interconnects
Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board...
US-9,842,818 Variable ball height on ball grid array packages by solder paste transfer
BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold...
US-9,842,817 Solder bump stretching method and device for performing the same
A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are...
US-9,842,816 Conductive pad structure for hybrid bonding and methods of forming same
A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the...
US-9,842,815 Semiconductor device and method of manufacture
A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer,...
US-9,842,814 Integrated RF subsystem
There is provided an integrated RF subsystem including a chip substrate, a circuit patterned on a first surface of the chip substrate, a probe electrically...
US-9,842,813 Tranmission line bridge interconnects
In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge...
US-9,842,812 Self-destructing chip
Embodiments herein provide for a self-destructing chip including at least a first die and a second die. The first die includes an electronic circuit, and the...
US-9,842,811 Heat-dissipating semiconductor package for lessening package warpage
A heat-dissipating semiconductor package includes a substrate, a chip, a first encapsulation body, a second encapsulation body and a heat sink. The substrate...
US-9,842,810 Tiled-stress-alleviating pad structure
Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad...
US-9,842,809 Semiconductor packages having EMI shielding parts and methods of fabricating the same
A semiconductor package may include a semiconductor device mounted on a package substrate, a conductive roof located over the semiconductor device, a plurality...
US-9,842,808 Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between...
A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the...
US-9,842,807 Integrated circuit assembly
An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top...
US-9,842,805 Drive-in Mn before copper plating
Techniques for forming Cu interconnects in a dielectric are provided. In one aspect, a method of forming a Cu interconnect structure includes: forming at least...
US-9,842,804 Methods for reducing dual damascene distortion
An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value...
US-9,842,803 Semiconductor devices including gaps between conductive patterns
Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable...
US-9,842,802 Integrated circuit device featuring an antifuse and method of making same
One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first...
US-9,842,801 Self-aligned via and air gap
Provided are approaches for forming a self-aligned via and an air gap within a semiconductor device. Specifically, one approach produces a device having: a...
US-9,842,800 Forming interconnect structures utilizing subtractive paterning techniques
Methods of forming conductive interconnect structures are described. Those methods/structures may include providing a package substrate comprising a substrate...
US-9,842,799 Semiconductor packages including upper and lower packages and heat dissipation parts
A semiconductor package includes a lower package with a lower substrate and a lower semiconductor chip. A heat dissipation part is provided adjacent to a side...
US-9,842,798 Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An...
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