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Patent # Description
US-9,842,797 Stacked die power converter
A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor...
US-9,842,796 Electronic module including a device for dissipating heat generated by a semiconductor unit situated in a...
An electronic module including a semiconductor unit situated in a plastic housing, an electrically conductive plate system, via which the semiconductor unit may...
US-9,842,795 Lead and lead frame for power package
A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a...
US-9,842,794 Semiconductor package with integrated heatsink
One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes...
US-9,842,792 Method of producing a semiconductor package
A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes...
US-9,842,791 Base with heat absorber and heat dissipating module having the base
An exemplary base includes a heat absorber and clips attached to the heat absorber. The heat absorber includes a top surface and a bottom surface. A pair of...
US-9,842,790 Conductive line system and process
A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each...
US-9,842,789 Electronic component package and method of manufacturing the same
An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on...
US-9,842,788 Underfill control structures and method
A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an...
US-9,842,787 Electronic element package and method for manufacturing the same
The present disclosure relates to an electronic element package and a method of manufacturing the same. The electronic element package includes a substrate, an...
US-9,842,786 Semiconductor device
A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from...
US-9,842,785 Apparatus and method for verification of bonding alignment
Presented herein is a device comprising a common node disposed in a first wafer a test node disposed in a first wafer and having a plurality of test pads...
US-9,842,784 System and methods for producing modular stacked integrated circuits
A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the...
US-9,842,783 Polishing method and polishing apparatus
A polishing method capable of obtaining an accurate thickness of a silicon layer during polishing of a substrate and determining an accurate polishing end point...
US-9,842,782 Intermediate structure for transfer, method for preparing micro-device for transfer, and method for processing...
A method for preparing a plurality of micro-devices for transfer includes temporarily bonding the micro-devices onto a carrier substrate; testing the...
US-9,842,781 Electrostatic chuck system and method of manufacturing organic light-emitting display apparatus by using the same
An electrostatic chuck system includes an electrostatic chuck with a plurality of unit chucks supporting a display substrate, an optical photomask on the...
US-9,842,780 Method for wafer level reliability
A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 .ANG. on a...
US-9,842,779 Method of evaluating metal contamination in semiconductor wafer and method of manufacturing semiconductor wafer
An aspect of the present invention relates to a method of evaluating metal contamination in a semiconductor wafer that has been subjected to a heat treatment,...
US-9,842,778 Method of fabricating FinFET structure
A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation...
US-9,842,777 Semiconductor devices comprising multiple channels and method of making same
The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a...
US-9,842,776 Integrated circuits and molding approaches therefor
Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable...
US-9,842,775 Semiconductor device and method of forming a thin wafer without a carrier
A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate....
US-9,842,774 Through substrate via structure for noise reduction
A semiconductor device includes a substrate and a through substrate via structure. The substrate has a through via hole. The through substrate via structure is...
US-9,842,773 Semiconductor device and method of manufacturing the same semiconductor device
The semiconductor device includes a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the...
US-9,842,772 Method of etching
A method is for etching a semiconductor substrate to reveal one or more features buried in the substrate. The method includes performing a first etch step using...
US-9,842,771 Semiconductor device and fabrication method thereof and semiconductor structure
A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding...
US-9,842,770 Reflow enhancement layer for metallization structures
A reflow enhancement layer is formed in an opening prior to forming and reflowing a contact metal or metal alloy. The reflow enhancement layer facilitates the...
US-9,842,769 Method of enabling seamless cobalt gap-fill
Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact...
US-9,842,768 Method for forming semiconductor device structure
A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer and a first conductive structure over a...
US-9,842,767 Method of forming an interconnection
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a...
US-9,842,766 Semiconductor device and method for fabricating semiconductor device
A semiconductor device according to an embodiment, includes a plurality of wires, a first dielectric film, and a second dielectric film. The plurality of wires...
US-9,842,765 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a dielectric...
US-9,842,764 Display device using semiconductor light emitting devices and method for manufacturing the same
A display device including a plurality of semiconductor light emitting devices on a wiring substrate; a connection part on the wiring substrate and configured...
US-9,842,763 Method for manufacturing bonded wafer
A method for manufacturing a bonded wafer using a base wafer which is an epitaxial wafer produced by a method including at least one of: (1) setting a chamfer...
US-9,842,762 Method of manufacturing a semiconductor wafer having an SOI configuration
The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including...
US-9,842,761 Mechanisms for forming FinFETs with different fin heights
A semiconductor device is provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and a second fin partially...
US-9,842,760 Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. First, a substrate having a fin-shaped structure thereon is provided, a spacer is formed adjacent to...
US-9,842,759 Support ring with masked edge
A support ring for semiconductor processing is provided. The support ring includes a ring shaped body defined by an inner edge and an outer edge. The inner edge...
US-9,842,758 Package structure and fabrication method thereof
A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing...
US-9,842,757 Robot and adaptive placement system and method
A method including moving a substrate, located on a first end effector of a robot, from a first location towards a second location by the robot; determining...
US-9,842,756 Integrated systems for interfacing with substrate container storage systems
A storage system and methods for operating a storage system are disclosed. The storage system includes a plurality of storage shelves, and each of storage...
US-9,842,755 Method and system for naturally oxidizing a substrate
A system and method for treating a substrate in a reaction chamber. A transfer chamber is arranged between a first lock and a second lock, wherein the second...
US-9,842,754 Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory...
In the present invention, a substrate is placed at a predetermined position on a substrate support even though the substrate is deviated on a substrate transfer...
US-9,842,753 Absorbing lamphead face
The embodiments described herein generally relate to a lamphead assembly with an absorbing upper surface in a thermal processing chamber. In one embodiment, a...
US-9,842,752 Optical heat source with restricted wavelengths for process heating
A semiconductor manufacturing system or process, such as an ion implantation system, apparatus and method, including a component or step for heating a...
US-9,842,751 Substrate liquid processing apparatus
Disclosed is a substrate liquid processing apparatus. The apparatus includes: a substrate holding unit configured to hold a substrate horizontally; a nozzle...
US-9,842,750 Plasma processing method
Disclosed is a plasma processing device that provides an object to be treated with plasma treatment. A wafer as an object to be treated, which is attached on...
US-9,842,749 Plasma assisted method of accurate alignment and pre-bonding for microstructure including glass or quartz chip
The plasma-assisted method of precise alignment and pre-bonding for microstructure of glass and quartz microchip belongs to micromachining and bonding...
US-9,842,748 Flow controlled liner having spatially distributed gas passages
Embodiments of the present disclosure provide a liner assembly including a plurality of individually separated gas passages. The liner assembly enables...
US-9,842,747 Substrate liquid processing apparatus, exhaust switching unit and substrate liquid processing method
A substrate liquid processing apparatus includes a liquid processing unit that processes a substrate with processing liquids, an exhaust pipe, individual...
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