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Patent # Description
US-9,842,087 Multi-sensor measuring method and system
The measurement system having multiple sensors for sensing the same physical magnitude comprises at least one set of n redundant sensors or of models...
US-9,842,086 Calculation device, calculation method, and program
A first calculation unit is capable of calculating f(x).sup.bx.sub.1 and sets a calculation result of f(x).sup.bx.sub.1 to u, and a second calculation unit is...
US-9,842,085 Adder capable of supporting addition and subtraction of up to n-bit data and method of supporting addition and...
An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to...
US-9,842,084 Write cache and write-hole recovery in distributed raid over shared multi-queue storage devices
A method for data storage includes, in a system that includes multiple servers, multiple multi-queue storage devices and at least one storage controller that...
US-9,842,083 Using completion queues for RDMA event detection
Systems and methods for using completion queues for Remote Direct Memory Access (RDMA) event detection. An example method may comprise: receiving a request to...
US-9,842,082 Dynamically updating logical identifiers of cores of a processor
In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to...
US-9,842,081 Implementing modal selection of bimodal coherent accelerator
A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a...
US-9,842,080 Bidirectional communication method and bidirectional communication apparatus using the same
A communication method according to the present embodiment is a communication method between a first side and a second side operating with a clock provided by...
US-9,842,079 Communication apparatus, communication method, and computer readable medium
A gateway apparatus (103) receives a request frame transmitted from a system controller (101) to an indoor unit 1 (111), and determines whether a sensor...
US-9,842,078 Data transmission architecture
A data transmission architecture includes a local system and a peripheral system. A core computing unit and the peripheral hub of the local system integrate...
US-9,842,077 Control server system with a switch and comparing circuit for controlling a trigger time for buffer and power...
A control system includes a switch circuit, a buffering circuit, and a motherboard. The switch circuit is configured to output a switch signal having a trigger...
US-9,842,076 Switchless USB C-connector hub
A USB hub integrated circuit device, comprising USB hub logic comprising a plurality USB ports, wherein at least one port comprises a pair of bi-directional...
US-9,842,075 Presenting multiple endpoints from an enhanced PCI express endpoint device
A system that provides virtualized computing resources to clients or subscribers may include an enhanced PCIe endpoint device on which an emulation processor...
US-9,842,074 Tag allocation for non-posted commands in a PCIe application layer
Embodiments herein provide for tag allocation in a PCIe application layer. In one embodiment, an apparatus operable to interface with a plurality of virtual...
US-9,842,073 N-phase signal transition alignment
System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information...
US-9,842,072 Systems and methods for implementing a user mode virtual serial communications port emulator
Systems and methods for implementing a user mode virtual serial communications port emulator are disclosed herein. According to an aspect, a method for a...
US-9,842,071 Multi-channel I.sup.2S transmit control system and method
A serial peripheral interface is configurable to operate in a I.sup.2S transmission mode. The interface has a transmission unit connected with external pins for...
US-9,842,070 Storage apparatus, control apparatus and computer-readable recording medium having stored therein control program
A storage apparatus includes a plurality of control devices configured to control access a plurality of storage devices, and a relay apparatus including a...
US-9,842,069 Hardware accelerator and chip
Present invention disclose a hardware accelerator and a chip, and the hardware accelerator includes: an interface circuit and an accelerator core coupled to the...
US-9,842,068 Methods of bus arbitration for low power memory access
Systems and method for arbitrating requests to a shared memory system for reducing power consumption of memory accesses, comprises determining power modes...
US-9,842,067 Processor communications
A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral...
US-9,842,066 Integrated circuit comprising an IO buffer driver and method therefor
An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is...
US-9,842,065 Virtualization-based platform protection technology
A data processing system (DPS) uses platform protection technology (PPT) to protect some or all of the code and data belonging to certain software modules. The...
US-9,842,064 Electronic apparatus and management method thereof
An electronic apparatus operating with a memory includes an operating module, a management module, a database and a filtering module. When the operating module...
US-9,842,063 Encrypting data for storage in a dispersed storage network
A method includes retrieving a plurality of secure data packages from storage units. The method further includes separating the secure data packages into masked...
US-9,842,062 Backup accessible by subset of related devices
Some embodiments provide, for a particular device in a set of related devices, a method for backing up data synchronized between the devices. The method...
US-9,842,061 Implementing advanced caching
Embodiments are disclosed for implementing a priority queue in a storage device, e.g., a solid state drive. At least some of the embodiments can use an...
US-9,842,060 Cache over-provisioning in a data storage device
A hybrid data storage device disclosed herein includes a main data store, one or more data storage caches, and a data storage cache management sub-system. The...
US-9,842,059 Wear leveling in storage devices
A system may include a plurality of memory cells and a processor. The plurality of memory cells may include a plurality of physical locations at which data is...
US-9,842,058 Locking entries into translation lookaside buffers
Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional...
US-9,842,057 Storage apparatus, storage system, and data read method
There is provided a storage apparatus connected to a storage device that stores data and a cache device used as a temporary storage area of the data. The...
US-9,842,056 Systems and methods for non-blocking implementation of cache flush instructions
Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a...
US-9,842,055 Address translation cache that supports simultaneous invalidation of common context entries
A processor includes a mapping module that maps architectural virtual processor identifiers to non-architectural global identifiers and maps architectural...
US-9,842,054 Computing device and method for processing data in cache memory of the computing device
In a method for processing cache data of a computing device, a storage space of the storage device is divided into sections, and a section number of each data...
US-9,842,053 Systems and methods for persistent cache logging
A cache log module stores an ordered log of cache storage operations sequentially within the physical address space of a non-volatile storage device. The log...
US-9,842,052 Selective allocation of CPU cache slices to database objects
A central processing unit (CPU) forming part of a computing device, initiates execution of code associated with each of a plurality of objects used by a worker...
US-9,842,051 Managing aliasing in a virtually indexed physically tagged cache
A circuit includes a Virtually Indexed Physically Tagged (VIPT) cache and a cache coherency circuit. The VIPT cache includes a plurality of sets and performs a...
US-9,842,050 Add-on memory coherence directory
A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the...
US-9,842,049 Data deployment determination apparatus, data deployment determination program, and data deployment...
A data deployment determination apparatus includes a correlation information creation processor that creates correlation information in which addresses...
US-9,842,048 Systems, methods, and computer readable media for digital radio broadcast receiver memory and power reduction
A method of block deinterleaving data received at a digital radio broadcast receiver is described. The method includes providing a block of memory having a...
US-9,842,047 Non-sequential write for sequential read back
A storage device controller addresses consecutively-addressed portions of incoming data to consecutive data tracks on a storage medium and writes the...
US-9,842,046 Processing memory access instructions that have duplicate memory indices
A method of an aspect includes receiving an instruction indicating a first source packed memory indices, a second source packed data operation mask, and a...
US-9,842,045 Failure recovery testing framework for microservice-based applications
Systems and methods are provided for resiliency testing microservice-based applications. For example, a method for resiliency testing an application includes...
US-9,842,044 Commit sensitive tests
A method, system and computer program product for commit sensitive testing is provided. The method includes applying a full set of different tests to an...
US-9,842,043 System and method to implement an electronic document based automated testing of a software application
A system for testing a software application includes (a) a memory unit includes a database and a set of modules; and (b) a processor that executes the set of...
US-9,842,042 Datacenter management computing system
A system may include an active first point of deployment (POD) configured to provide a specified business functionality and may include a first server and a...
US-9,842,041 Approximation of datastore storing indexed data entries
The technology can compute an approximation of a datastore storing a multiplicity of indexed data. An example method can a template including programming logic...
US-9,842,040 Tracking core-level instruction set capabilities in a chip multiprocessor
Techniques described herein generally relate to a task management system for a chip multiprocessor having multiple processor cores. The task management system...
US-9,842,039 Predictive load scaling for services
Embodiments are directed to determining an optimal number of concurrently running cloud resource instances and to providing an interactive interface that shows...
US-9,842,038 Method and system for advanced fail data transfer mechanisms
Embodiments of the present invention utilize a dual buffer size threshold system for raising interrupts that allows DUT testing systems to perform real-time...
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