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Patent # Description
US-9,853,143 Closed cell lateral MOSFET using silicide source and body regions with self-aligned contacts
A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions formed...
US-9,853,142 Method of manufacturing a trench FET having a merged gate dielectric
In one implementation, a method for fabricating a trench FET includes providing a semiconductor substrate including a drain region and a drift zone over the...
US-9,853,141 Semiconductor device with front and rear surface electrodes on a substrate having element and circumferential...
Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an...
US-9,853,140 Adaptive charge balanced MOSFET techniques
An adaptive charge balanced MOSFET device includes a field plate stacks, a gate structure, a source region, a drift region and a body region. The gate structure...
US-9,853,139 Semiconductor device and method for manufacturing the semiconductor device
A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided...
US-9,853,138 III-N based high power transistor with InAlGaN barrier
A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, a plurality of contact layers formed over portions of the...
US-9,853,137 Method for forming a semiconductor device and a semiconductor device
A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor...
US-9,853,136 Directed epitaxial heterojunction bipolar transistor
A directed epitaxial heterojunction bipolar transistor (HBT) structure is directly or indirectly formed on a GaAs substrate that is formed by a (100) face...
US-9,853,135 Tunnel field effect transistor (TFET) with lateral oxidation
A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide...
US-9,853,133 Method of manufacturing high resistivity silicon-on-insulator substrate
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a...
US-9,853,132 Nanosheet MOSFET with full-height air-gap spacer
A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a...
US-9,853,131 Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch
A method of forming an arrangement of active and inactive fins on a substrate, including forming at least three vertical fins on the substrate, forming a...
US-9,853,130 Method of modifying the strain state of a semiconducting structure with stacked transistor channels
A method of modifying a strain state of a first channel structure in a transistor is provided, said structure being formed from superposed semiconducting...
US-9,853,129 Forming non-line-of-sight source drain extension in an nMOS finFET using n-doped selective epitaxial growth
A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the...
US-9,853,128 Devices and methods of forming unmerged epitaxy for FinFET device
Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a...
US-9,853,127 Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first...
US-9,853,126 Semiconductor device with vertical gate and method of manufacturing the same
A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed,...
US-9,853,125 Vertical tunneling field-effect transistor cell and fabricating the same
A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the...
US-9,853,124 Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers
Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered...
US-9,853,123 Semiconductor structure and fabrication method thereof
A semiconductor structure includes a substrate having thereon a dielectric layer. An opening is formed in the dielectric layer. The opening includes a bottom...
US-9,853,122 Semiconductor device fabrication method and semiconductor device
A method of fabricating a semiconductor device includes forming a first semiconductor region at a front surface of a substrate, the first semiconductor region...
US-9,853,121 Method of fabricating a lateral insulated gate bipolar transistor
A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and...
US-9,853,120 Trench Schottky rectifier device and method for manufacturing the same
A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity...
US-9,853,119 Integration of an auxiliary device with a clamping device in a transient voltage suppressor
Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers...
US-9,853,118 Diode-based devices and methods for making the same
In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening...
US-9,853,117 Spacer chamfering gate stack scheme
A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are...
US-9,853,116 Partial sacrificial dummy gate with CMOS device with high-k metal gate
A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial...
US-9,853,115 Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device...
US-9,853,114 Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same
A field effect transistor (FET) for an nFET and/or a pFET device including a fin having a stack of nanowire-like channel regions. The stack includes at least a...
US-9,853,113 Semiconductor device
A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first...
US-9,853,112 Device and method to connect gate regions separated using a gate cut
A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further...
US-9,853,111 Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device includes forming active fins on a substrate; forming source/drain regions on the active fins on both sides of a...
US-9,853,110 Method of forming a gate contact structure for a semiconductor device
One illustrative method disclosed includes, among other things, forming a gate contact opening in a layer of insulating material, performing at least one...
US-9,853,108 Nitride semiconductor device using insulating films having different bandgaps to enhance performance
The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a...
US-9,853,107 Selective epitaxially grown III-V materials based devices
An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material...
US-9,853,106 Nano-structure assembly and nano-device comprising same
Provided are a nano-structure assembly including an insulating substrate; and a nano-structure formed on the insulating substrate, and a nano-device including...
US-9,853,105 Semiconductor device and method of formation
A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second...
US-9,853,104 Hydrogenated graphene with surface doping and bandgap tunability
A graphene compound made from the method of preparing graphene flakes or chemical vapor deposition grown graphene films on a SiO.sub.2/Si substrate; exposing...
US-9,853,103 Pinched doped well for a junction field effect transistor (JFET) isolated from the substrate
A JFET structure may be formed such that the channel region is isolated from the substrate to reduce parasitic capacitance. For example, instead of using a deep...
US-9,853,102 Tunnel field-effect transistor
A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with...
US-9,853,101 Strained nanowire CMOS device and method of forming
Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial...
US-9,853,100 High voltage device and manufacturing method thereof
The present invention provides a high voltage device and manufacturing method thereof. The high voltage device includes: a semiconductor substrate, an isolation...
US-9,853,099 Double diffused metal oxide semiconductor device and manufacturing method thereof
The present invention provides a DMOS device and a manufacturing method thereof. The DMOS device includes: a substrate, an epitaxial layer, a high voltage well,...
US-9,853,098 Light emitting device and manufacturing method of the same
The present invention is directed to a light emitting device structured so as to increase the amount of light which is taken out in a certain direction after...
US-9,853,097 Organic light emitting diode display including pixel having shielding electrode
An organic light emitting display in which each pixel has a driving thin film transistor for adjusting the current flowing through an organic light emitting...
US-9,853,096 Display with inactive area surrounded by active area
A display may have an active area with an array of pixels to display images. An inactive area in the display may be formed from an opening in the active area....
US-9,853,095 Display device
A display device includes a first pixel and a second pixel arranged in a first or a second direction, each of them has a pixel electrode, a contact hole under...
US-9,853,094 Display device and method of manufacturing the same
A display device and manufacturing method thereof with a high level of reliability is provided without increasing the number of manufacturing processes. The...
US-9,853,093 Organic light emitting diode device
An OLED display includes a first substrate, a first electrode on the first substrate, a pixel defining layer having a first aperture exposing the first...
US-9,853,092 OLED display device having touch sensor and method of manufacturing the same
An OLED display device having a touch sensor is provided. The touch sensor includes a base layer; a plurality of first touch electrodes arranged in a first...
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